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Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs

Fayyaz, Asad; Castellazzi, Alberto; Romano, G.; Riccio, M.; Urresti, J.; Wright, N.

Authors

Asad Fayyaz eexaf12@exmail.nottingham.ac.uk

Alberto Castellazzi alberto.castellazzi@nottingham.ac.uk

G. Romano

M. Riccio

J. Urresti

N. Wright



Abstract

This paper investigates the effect of negative gate bias voltage (VGS) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device’s ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

Publication Date May 28, 2017
Peer Reviewed Peer Reviewed
APA6 Citation Fayyaz, A., Castellazzi, A., Romano, G., Riccio, M., Urresti, J., & Wright, N. (2017). Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs
Keywords avalanche ruggeddness; silicon carbide; unclamped inductive swithching; power MOSFET; robustness
Publisher URL http://ieeexplore.ieee.org/document/7988986/
Copyright Statement Copyright information regarding this work can be found at the following address: http://eprints.nottingh.../end_user_agreement.pdf
Additional Information doi:10.23919/ISPSD.2017.7988986

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Copyright Statement
Copyright information regarding this work can be found at the following address: http://eprints.nottingham.ac.uk/end_user_agreement.pdf





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