Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs

Fayyaz, Asad; Castellazzi, Alberto; Romano, G.; Riccio, M.; Urresti, J.; Wright, N.

Abstract

This paper investigates the effect of negative gate bias voltage (VGS) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device’s ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

Citation

Fayyaz, A., Castellazzi, A., Romano, G., Riccio, M., Urresti, J., & Wright, N. (2017). Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs.

• Conference Name: 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)
• End Date: Jun 1, 2017
• Acceptance Date: Mar 31, 2017
• Online Publication Date: Jun 24, 2017
• Publication Date: May 28, 2017
• Deposit Date: Feb 27, 2018
• Publicly Available Date: Feb 27, 2018
• Peer Reviewed: Peer Reviewed
• Keywords: avalanche ruggeddness; silicon carbide; unclamped inductive swithching; power MOSFET; robustness
• Public URL: https://nottingham-repository.worktribe.com/output/862170
• Publisher URL: http://ieeexplore.ieee.org/document/7988986/
• Additional Information: doi:10.23919/ISPSD.2017.7988986
• Contract Date: Feb 27, 2018