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10kV+ rated SiC n-IGBTs: novel collector side design approach breaking the trade-off between dV/dt and device efficiency

Almpanis, Ioannis; Evans, Paul; Antoniou, Marina; Gammon, Peter; Lee, Empringham; Undrea, Florin; Mawby, Philip; Lophitis, Neophytos


Ioannis Almpanis

Associate Professor

Marina Antoniou

Peter Gammon

Professor of Power Conversion Technologies

Florin Undrea

Philip Mawby


10kV+ rated 4H-Silicon Carbide (SiC) Insulated Gate Bipolar Transistors (IGBTs) have the potential to become the devices of choice in future Medium Voltage (MV) and High Voltage (HV) power converters. One significant performance concern of SiC IGBTs is the extremely fast collector voltage rise (dV/dt) observed during inductive turn-off, which can cause significant electromagnetic noise. Resolution of this at system level solutions might be possible with the use of complex circuitry, ultra-fast gate drivers or snubbers, which increase the losses and limit the theoretical gain achieved by using 4H-SiC. Studies on the physical mechanisms of high dV/dt in 4H-SiC IGBTs revealed the importance of collector side design in controlling the phenomenon. However, the proposed device design solutions, although improved the trade-off, did not decouple the achievable reduction in dV/dt from the impact on performance. In this paper we propose a new collector side design approach which allows the control of dv/dt independently from the device performance. Further, we demonstrate a reduction of dV/dt by 87% without degrading the high switching frequency capability of the device. The inductive turn-off process in 4H-SiC IGBTs has two distinct voltage rising phases, a slow and a fast. The first (slow) voltage rising phase initiates when the gate voltage falls below the threshold voltage terminating the channel electron injection. The space charge region starts expanding towards the collector side by removing holes at the space charge boundary. When the space charge region reaches the buffer layer, a second (fast) voltage rise phase begins. The second (fast) voltage rise phase is caused by the rather small amount of minority carriers (holes) present in the buffer. Increasing the concentration of minority carrier injection into the buffer is key in reducing the dV/dt but it comes at the cost of higher switching losses [1]-[4]. In [5] a two-step buffer was proposed, however it was shown that when both the turn-off switching loss and the dV/dt are reduced, the on-state voltage drop increases due to lower drift layer plasma concentration. Additionally, the dV/dt value achieved was still very high (>120kV/μs) even at 25A/cm 2 and is expected to be higher for higher current density. We propose having a two-step buffer and two-step drift region doping profile as shown in Fig. 1 (a) and Fig. 1 (b). The higher doped buffer region (HDB) prevents the depletion region from reaching through to the collector region during the forward (static) blocking. The lower doped buffer region (LDB) controls the plasma injection into the drift layer and the trade-off between on-state and switching losses. The higher doped drift region (HDD) is responsible for preventing the depletion region from punching-through to the buffer layer during the voltage rising phase of the inductive turn-off and therefore controls the dV/dt by increasing the amount of minority carriers to be removed. Finally, the lower doped drift region (LDD) controls the breakdown characteristics of the IGBT. As a result, the simple proposed device structure offers the advantage of the almost independent control of the trade-off between on-state and switching losses and dV/dt. In other words, the maximum switching frequency of the IGBT can be controlled by the LDB region without affecting the dV/dt, and thus decoupling these quantities. The switching circuit used is shown in Fig. 1(c). Fig. 2(a) shows the adjustment of dV/dt, by the HDD region parameters and in comparison with the conventional design. The amount of holes to be removed after the depletion of the lightly doped drift region (result not shown) can be effectively controlled offering controllability of the dV/dt. The reduction of dV/dt is 87% without affecting significantly the on-state voltage drop and turn-off switching losses by the HDD region parameters. Fig. 2(b) shows the adjustment of the trade-off between on-state voltage drop and turn-off switching losses by the LDB region parameters. A way to visualize the decoupling of the high dV/dt from the switching frequency is to plot the maximum switching frequency that can be achieved for a given power dissipation and the


Almpanis, I., Evans, P., Antoniou, M., Gammon, P., Lee, E., Undrea, F., …Lophitis, N. (2022). 10kV+ rated SiC n-IGBTs: novel collector side design approach breaking the trade-off between dV/dt and device efficiency.

Conference Name 19th International Conference on Silicon Carbide and Related Materials (ISCRM 2022)
Conference Location Davos, Switzerland
Start Date Sep 11, 2022
End Date Sep 16, 2022
Acceptance Date Jul 1, 2022
Publication Date Sep 16, 2022
Deposit Date Nov 3, 2022
Publisher Trans Tech Publications
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