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Two quadrant analogue squarer circuit based on MOS square-law characteristic

Craven, M.P.; Hayes-Gill, B.R.

Authors

M.P. Craven

B.R. Hayes-Gill

Abstract

A novel analogue CMOS circuit is presented which performs the arithmetical squaring of a voltage, using the square-law characteristic of the MOS transistor in saturation. The core circuit is constructed from four identical building blocks, which are connected so as to eliminate all unwanted offset terms. Simulation results from HSPICE are presented where the circuit is used for doubling the frequency of a sinusoidal input.

Journal Article Type Article
Publication Date 1991
Journal Electronics Letters
Print ISSN 0013-5194
Publisher Institution of Engineering and Technology
Peer Reviewed Peer Reviewed
Volume 27
Issue 25
Pages 2307–2308
DOI https://doi.org/10.1049/el%3A19911429
Publisher URL http://digital-library.theiet.org/content/journals/10.1049/el_19911429

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