Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion
(2020)
Conference Proceeding
Alqahtani, S., Zhu, Y., Shi, Q., Meng, X., & Wang, X. (2020). Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion. In 2020 International Conference on Field-Programmable Technology (ICFPT) (250-255). https://doi.org/10.1109/ICFPT51103.2020.00043
This paper proposes two hardware architectures for matrix inversion, through the use of single and double-precision floating-point representations. The architectures use a modified version of the Gauss-Jordan algorithm that accelerates the processing... Read More about Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion.