A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix Inversion
(2022)
Presentation / Conference Contribution
Alqahtani, S., Zhu, Y., Shi, Q., Meng, X., & Wang, X. (2022, December). A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix Inversion. Presented at FPT 2022 International Conference on Field Programmable Technology, Hong Kong
This paper introduces an efficient and customizable FPGA-based architecture for parallel matrix inversion. The capability of the proposed customizable architecture to adapt to different matrix sizes with low latency and effective resource utilization... Read More about A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix Inversion.