Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion
(2020)
Conference Proceeding
This paper proposes two hardware architectures for matrix inversion, through the use of single and double-precision floating-point representations. The architectures use a modified version of the Gauss-Jordan algorithm that accelerates the processing... Read More about Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion.