Low inductance 2.5kV packaging technology for SiC switches

Mouawad, Bassem; Li, Jianfeng; Castellazzi, Alberto; Johnson, Christopher Mark; Erlbacher, Tobias; Friedriches, Peter

Abstract

The switching speed of power semiconductors has reached levels where conventional semiconductors packages limit the achievable performance due to relatively high parasitic inductance and capacitance. This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to ac¬commodate 8 SiC JFETs and 4 SiC diodes. Electromagnetic simulation results reveal extremely low in¬ductance values of the major loops. Due to delay delivery of those custom ordered substrate and PCB, the prototyping samples of the designed module have yet been constructed. The up to date results including experimental construction, electrical and thermal performance of the samples will be presented at the conference.

Citation

Mouawad, B., Li, J., Castellazzi, A., Johnson, C. M., Erlbacher, T., & Friedriches, P. Low inductance 2.5kV packaging technology for SiC switches. Presented at 9th International Conference on Integrated Power Electronics Systems

• Conference Name: 9th International Conference on Integrated Power Electronics Systems
• End Date: Mar 10, 2016
• Acceptance Date: Mar 8, 2015
• Publication Date: Jan 1, 2016
• Deposit Date: Oct 3, 2016
• Peer Reviewed: Peer Reviewed
• Public URL: https://nottingham-repository.worktribe.com/output/980262
• Related Public URLs: https://conference.vde.com/cips/2016/Pages/Report.aspx
• Additional Information: Published in: ETG-Fb. 148: CIPS 2016; 9th International Conference on Integrated Power Electronics Systems, Proceedings March, 8 – 10, 2016, Nuremberg/Germany.; ; ETG-Fachberichte 2016, 586 pages, CD-Rom.; ISBN 9783800741717
• Contract Date: Oct 3, 2016