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Low parasitic inductance multi-chip SiC devices packaging technology

Li, Jianfeng; Mouawad, Bassem; Castellazzi, Alberto; Friedrichs, Peter; Johnson, Christopher Mark

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Authors

Jianfeng Li

Bassem Mouawad

Alberto Castellazzi

Peter Friedrichs

MARK JOHNSON MARK.JOHNSON@NOTTINGHAM.AC.UK
Professor of Advanced Power Conversion



Abstract

This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to accommodate 8 SiC JFETs and 4 SiC diodes. Electromagnetic simulation results reveal extremely low inductance values of the major loops. Then the prototyping of the designed package including the assembly process, all the electrical test to evaluate the electrical performance are presented.

Citation

Li, J., Mouawad, B., Castellazzi, A., Friedrichs, P., & Johnson, C. M. (in press). Low parasitic inductance multi-chip SiC devices packaging technology.

Conference Name 18th European Conference on Power Electronics and Applications
End Date Sep 9, 2016
Acceptance Date Mar 1, 2016
Deposit Date Oct 3, 2016
Peer Reviewed Peer Reviewed
Keywords Wide bandgap devices, High frequency power converter, Silicon Carbide (SiC), Packaging, high voltage power converters, JFET, Wind energy
Public URL https://nottingham-repository.worktribe.com/output/774488
Related Public URLs http://www.epe2016.com/
Contract Date Oct 3, 2016

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