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Parametric study of optimum gate-resistance for performance and short-circuit robustness of novel half-bridge IGBT modules

Cheraghinezhad, Alireza; Hussein, Abdallah; Castellazzi, Alberto; Saito, Katsuaki

Parametric study of optimum gate-resistance for performance and short-circuit robustness of novel half-bridge IGBT modules Thumbnail


Authors

Alireza Cheraghinezhad

Abdallah Hussein

Alberto Castellazzi

Katsuaki Saito



Abstract

This paper jointly investigates the switching performance and the short-circuit (S.C) turn off behavior of a novel half-bridge (2in1) IGBT power module concept with the low stray inductance (Lσ), which has been available in the market since 2015. Since this package was designed for improving the performance of Si-based switches and is a pioneering solution for designing WBG switches through reducing the Lσ of the switch itself, investigations of S.C are an important task for both researchers and designers. The performance of a Half-bridge (2in1) Silicon N-channel IGBT has been examined with different temperatures, switching transients and testing under S.C conditions, where the extracted results offer a clear overview of S.C of Half-bridge (2in1) package and trade-offs between switch losses and short-circuit safe operating area (SCSOA), and finally prevention of false turn-on after short-circuiting due to Lσ.

Citation

Cheraghinezhad, A., Hussein, A., Castellazzi, A., & Saito, K. (2018, November). Parametric study of optimum gate-resistance for performance and short-circuit robustness of novel half-bridge IGBT modules. Presented at 5th International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles (ESARS) and International Transportation Electrification Conference (ITECH), Nottingham, UK

Presentation Conference Type Edited Proceedings
Conference Name 5th International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles (ESARS) and International Transportation Electrification Conference (ITECH)
Start Date Nov 7, 2018
End Date Nov 9, 2018
Acceptance Date Jul 26, 2018
Online Publication Date Jan 13, 2019
Publication Date Nov 9, 2018
Deposit Date Oct 26, 2018
Publicly Available Date Oct 26, 2018
Publisher Institute of Electrical and Electronics Engineers
Peer Reviewed Peer Reviewed
DOI https://doi.org/10.1109/ESARS-ITEC.2018.8607621
Public URL https://nottingham-repository.worktribe.com/output/1194654
Publisher URL https://ieeexplore.ieee.org/document/8607621
Related Public URLs http://www.esars.eu/wp2018/
Contract Date Oct 26, 2018

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