Co-design/simulation of flip-chip assembly for high voltage IGBT packages

Rajaguru, P.; Bailey, Christopher; Aliyu, Attahir Murtala; Castellazzi, Alberto; Pathirana, V.; Udugampola, N.; Trajkovic, T.; Udrea, F.; Mitchelson, P.D.; Elliot, A.D.T.

Abstract

This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue.

Citation

Rajaguru, P., Bailey, C., Aliyu, A. M., Castellazzi, A., Pathirana, V., Udugampola, N., Trajkovic, T., Udrea, F., Mitchelson, P., & Elliot, A. Co-design/simulation of flip-chip assembly for high voltage IGBT packages. Presented at 23rd International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2017

• Conference Name: 23rd International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2017
• End Date: Sep 29, 2018
• Acceptance Date: Jun 16, 2017
• Online Publication Date: Dec 25, 2017
• Publication Date: Sep 27, 2017
• Deposit Date: May 10, 2018
• Publicly Available Date: May 10, 2018
• Peer Reviewed: Peer Reviewed
• Public URL: https://nottingham-repository.worktribe.com/output/884676
• Publisher URL: https://ieeexplore.ieee.org/document/8233847/
• Additional Information: doi:10.1109/THERMINIC.2017.8233847
• Contract Date: May 10, 2018