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Co-design/simulation of flip-chip assembly for high voltage IGBT packages

Rajaguru, P.; Bailey, Christopher; Aliyu, Attahir Murtala; Castellazzi, Alberto; Pathirana, V.; Udugampola, N.; Trajkovic, T.; Udrea, F.; Mitchelson, P.D.; Elliot, A.D.T.

Authors

P. Rajaguru

Christopher Bailey

Attahir Murtala Aliyu

Alberto Castellazzi alberto.castellazzi@nottingham.ac.uk

V. Pathirana

N. Udugampola

T. Trajkovic

F. Udrea

P.D. Mitchelson

A.D.T. Elliot



Abstract

This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue.

Publication Date Sep 27, 2017
Peer Reviewed Peer Reviewed
APA6 Citation Rajaguru, P., Bailey, C., Aliyu, A. M., Castellazzi, A., Pathirana, V., Udugampola, N., …Elliot, A. (2017). Co-design/simulation of flip-chip assembly for high voltage IGBT packages
Publisher URL https://ieeexplore.ieee.org/document/8233847/
Copyright Statement Copyright information regarding this work can be found at the following address: http://eprints.nottingh.../end_user_agreement.pdf
Additional Information doi:10.1109/THERMINIC.2017.8233847

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Co-DesignSimulation of Flip-Chip Assembly for High Voltage IGBT Packages.pdf (777 Kb)
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Copyright Statement
Copyright information regarding this work can be found at the following address: http://eprints.nottingham.ac.uk/end_user_agreement.pdf





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