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Co-design/simulation of flip-chip assembly for high voltage IGBT packages

Rajaguru, P.; Bailey, Christopher; Aliyu, Attahir Murtala; Castellazzi, Alberto; Pathirana, V.; Udugampola, N.; Trajkovic, T.; Udrea, F.; Mitchelson, P.D.; Elliot, A.D.T.


P. Rajaguru

Christopher Bailey

Attahir Murtala Aliyu

Alberto Castellazzi

V. Pathirana

N. Udugampola

T. Trajkovic

F. Udrea

P.D. Mitchelson

A.D.T. Elliot


This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue.


Rajaguru, P., Bailey, C., Aliyu, A. M., Castellazzi, A., Pathirana, V., Udugampola, N., …Elliot, A. (2017). Co-design/simulation of flip-chip assembly for high voltage IGBT packages.

Conference Name 23rd International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2017
End Date Sep 29, 2018
Acceptance Date Jun 16, 2017
Online Publication Date Dec 25, 2017
Publication Date Sep 27, 2017
Deposit Date May 10, 2018
Publicly Available Date May 10, 2018
Peer Reviewed Peer Reviewed
Public URL
Publisher URL
Additional Information doi:10.1109/THERMINIC.2017.8233847


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