Experimental study of the short-circuit performance for a 600V normally-off p-gate GaN HEMT

In this paper, the short-circuit robustness of a normally-off GaN HEMT is investigated in relation to applied bias conditions and pulse duration. The results align with previous studies on normally-on devices in highlighting an electrical type of failure. Here, however, the relevance of the specific gate-drive circuit design and corresponding device operational conditions is demonstrated. A gate-bias dependence (GBD) of the failure, correlated to the applied drain-source voltage, is introduced as a novel specific feature for the p-Gate type device.


I. INTRODUCTION
Semiconductor devices with higher efficiency and reliability are significant milestone for power electronic applications (PEA) in the recent decade. Therefore, the high electron mobility transistor (HEMT), which is a wide band gap (WBG) semiconductor based on an AlGaN/GaN heterojunction, exhibits a promising solution. The unique functionality and characteristics of a GaN HEMT, in comparison to a Si MOSFET or IGBT device, lead to several advantages in the application. On the other hand, in most PEAs the switching devices are required to exhibit a normally-off operation. The usage of insulated-or p-doped gates (p-gate) [1] is one of the key technological solutions to achieve that.
In typical PEAs, a number of overload operational conditions have to be considered to ensure the device-and system/circuit robustness. Typically, this conditions are managed by system-level failure-detection and shut-down mechanisms to avoid destructions. Therefore, a crucial device withstand capability is required, to guarantee their intervention. The shortcircuit (SC) robustness is a very important feature of power transistors, strictly required by a number of applications (e.g., motor drives). The common minimum requirement is to withstand a short-circuit with 50% of the maximum breakdownvoltage for an SC duration of 10 µs. During an SC the device has to be capable of a high power dissipation, that eventually leads to an excessive self-heating related failure. A previous publication of normally-on GaN HEMT SC robustness [2] concluded the failure to be an electrical effect rather than an impact of a thermal issue. It is predicted, that the electrical impact occurs due to an accumulation of holes under the gate, which generates localised high electric fields and causes premature breakdown. Furthermore, the study determined a dependency of the time to failure, which is correlated to the gate-bias.
In this paper, a comprehensive experimental study of a normally-off p-gate HEMT is carried out. The test set-up is presented in chapter II and therefore the impact on the SC behaviour in chapter III. The SC robustness is investigated and presented according to the applied drain-source voltage in chapter IV and the SC duration in chapter V. Furthermore, during the study a variation of the gate-bias occurred, which correlates to the drain-source voltage. The characteristic and impact of this gate-bias dependence (GBD) is as a novelty introduced in chapter VI

II. MEASURMEMENT SET-UP
To determine the SC capability of the device, a measurement set-up composed of three major parts is used, as illustrated in Fig. 1. The SC duration can be adjusted by applying a voltage-pulse of a variable time (t SC ) on the gatedriver that further transmits an equivalent power-pulse to the gate for biasing the DUT in on-state. Feedback related effects during the SC failure can lead to driver destruction, therefore the gate-loop is galvanic (optical) decoupled. The device under test (DUT) is low inductive linked with an external source and interconnected stabilisation capacitor in the power-path. Hence, the drain-source voltage V DS can be assumed constant due to the large capacitance value.
Driving a p-gate HEMT features the existence of an onstate forward gate-current I G . The amount of the current Fig. 1: Test set-up, composed of: a galvanic (optical) decoupled gate-driver, a modulation-network of the gate-signal (common used in p-gate GaN HEMT applications), and a power-path with the device under test (DUT) I G can be adjusted with an appropriate gate-resistance R G . Consequently, the gate-source voltage V GS is set by I G with the equivalent voltage drop over R G . Therefore, as part of the gate-drive circuit, a modulation-network is used. This topology ensures a, with the usage in PEAs, comparable gatebias condition of the SC behaviour. Furthermore, the network provides optimised transient on-and off-state bias conditions of the DUT which are illustrated in Fig. 2 (bottom).

III. SC BEHAVIOUR AND TEST CONDITIONS
Various influences on the SC behaviour, related to the impact of the gate-drive circuit, can be captured. In the following, the relations are exemplary described, together with the extent of variation in the gate-drive circuit.
The waveform of the drain-current I D is depicted in Fig. 2 (top), with the respective V GS in Fig. 2 (bottom), serving as the impact exemplification. In the first time interval t 1 of the SC, a steep rise of the current I D occurs. The slope is mainly determined by the applied voltage V DS and the parasitic inductance of the SC loop. The p-gate structurally lacks a capacitive nature, therefore V GS is equal to the value of the drive-voltage V GS,peak = V DD . During the second time interval t 2 the voltage converge to its saturation value V GS,sat , in accordance to the functionally of the gate-drive circuit. Therefore, the current I D tends to decrease, which is further gained due to the impact of the self-heating. The issue of selfheating is related to an excessive power-dissipation and occurs as a thermal mobility degeneration [3]. In the last interval t 3 , the temperature within the device reaches a stable value, which leads to a respective saturation of the current I D,sat .
To cover the impact of the gate-drive circuit, a variation of test conditions is carried out. These test conditions are , an insignificant nominal reduction of on-state performance is predicted. Therefore, condition A corresponds to a high and B to a low value within this range, in order to investigate transferability on the SC performance and the capability respectively. To investigate the implication of V DD , the characteristics of condition C, which exhibits a lower value, are compared to condition B. In order to keep a comparable low bias current I G condition, the value of R G is reduced. Due to the GBD (as extensively explained in chapter VI) a decrease of V GS , correlated to an increase of V DS , can be observed. For comparability of p-and insulatedgate devices, the aim of condition D is to disregard the GBD. Therefore, in all terms of operation, an adjustment of R G is necessary to ensure a constant operation point.

IV. VOLTAGE TO FAILURE
The procedure of investigating the voltage restricted SC capability (see TABLE III V DS , until a failure occurs. Reaching the voltage restriction leads, in all conditions, to a device destruction within a few hundred nanoseconds. The device withstands the required SC duration for voltages V DS below the failure-voltage, therefore a significant thermal related failure can be neglected. Condition A withstands voltages until V DS = 340 V , whereas with condition B V DS = 390 V and with C up to V DS = 440 V is achieved. The earlier restriction of condition A in comparison to B, can be referred to the gate-current and is further detailed in chapter V. The current I D and the corresponding V GS waveforms for conditions B and C are depicted in Fig. 3. Therefore, the major difference is related to the initial value of the current I D,peak , see Fig. 3 (bottom). The carrier density affects the magnitude of the electrical field, which leads to an electrical breakdown in the structure for an exceedance of a critical value.
Furthermore, the range of voltage withstand capability, defined as ratio of failure-and the nominal breakdown voltage, diverse from approximately 60% up to 75% regarding the condition variation.

V. TIME TO FAILURE
The investigation of the SC duration capability (see TA-BLE III) is similar to the procedure for the voltage restriction. Therefore, the minimum required voltage V DS is kept constant and the time t SC is stepwise increased, until a failure occurs.
For condition C, an SC duration related restriction has not been observed. The waveform of the current I D is depicted in Fig. 4 (top), together with an estimation of the junctiontemperature in Fig. 4 (bottom). The temperature is determined with a numerical 3D temperature simulator which is presented  in [4]. The temperature settles for t SC ≥ 160 µs. An abrupt thermal related failure for higher durations is not expected, based on the results of this investigation respectively the performed operation condition.
For conditions A and B, a clear limitation of the SC duration is observed. The comparison with condition C further emphasizes that the failure is mainly related to the initial value of the current I D,peak (see chapter IV). Considering equal peak values I D,peak , in terms of condition A and B, an underlying limitation can be observed. The current I D waveform, for these two conditions within the last measurement before device destruction are depicted in Fig. 5 (top). Whereas the progression of I D is identical, the main difference can be observed at the gate-bias current I G . The respective waveforms of I G are depicted in Fig. 5 (bottom). The value of I G for condition A is one order of magnitude higher than in B. The injection of holes into the gate increases with the amount of the current I G . Therefore, an assumption of hole accumulation under the gate [2] can be made.

VI. GATE-BIAS DEPENDENCE
The SC behaviour of conditions B and D, for two different V DS , shows the significant characteristics of the GBD. Therefore, depicted in Fig. 6 (top), the zoom into the SC saturation region of I D the corresponding V GS (bottom). Comparing the current saturation values I D,sat at a specific voltage (e.g V DS = 100 V ), indicates a significant lowering for condition B. This characteristic are further observed for the value of the saturation voltage V GS,sat . Furthermore, for both conditions an approximately identical lowering of the current saturation values I D,sat , between the two different voltages (e.g. V DS = 100 V to V DS = 200 V ), occurs. According to the specific aim of condition D (see chapter III) a constant value of V GS,sat is achieved, whereas a V DS dependency occurs in case of condition B. However, the change of I D,sat , for a constant bias at condition D, also refers to a thermal mobility degeneration due to excessive power dissipation [3], as discussed in chapter III. Consequently, the further difference of the saturation values between conditions B with D relates to the impact of the GBD.
For an ideally constant current I D , the power dissipation behaves linear within the device, at an increase of voltage V DS . According to the thermal mobility degradation a non-uniform power dissipation occurs. Due to the GBD, a further gain of non-uniformity, for the operation of the p-gate HEMT, can be observed. The extent is illustrated as the percentage change of the dissipated power P D in Fig. 7 (top) and current I G (bottom), as function of V DS within the minimum required range. Therefore, the percentage change is defined as the ratio of saturation values (at t 3 , referring to the definition in chapter III) and the respective low voltage SC value. The forced increase of I G in condition D, in order to achieve a constant operation point, leads to a voltage related failure at V DS = 225 V . Therefore, measurements of higher V DS values could not be achieved. Therefore, the existence of the early failure confirms the observations obtained in chapter V. However, the GBD manifests itself in an unintended increase of I G approximately (4% · I G ) / (100 V ) for V DS ≥ 125 V . Furthermore, the pgate HEMT provides, for increasing values of the drain-source voltage, a respective self-contained lowering of performancerelated temperature gain.  CONCLUSION This paper has shown that the short-circuit withstand capability of p-Gate GaN HEMTs is mainly limited by the initial drain-current peak and the value of the gate-current. Both factors are strongly dependent on the design of the gatedrive circuit: optimised design can yield voltage robustness up to 75%, with very long pulse widths for lower values. The observed gate-bias dependence exhibits a self-protecting decrease of the current and power dissipation level during the pulse. Due to this, higher short-circuit capability is achieved if the drain-current peak and gate-current value is kept low, for increased voltages.