Interleaved Switched-Capacitor Bidirectional DC-DC Converter With Wide Voltage-Gain Range for Energy Storage Systems

In this paper, an interleaved switched-capacitor bidirectional dc-dc converter with a high step-up/step-down voltage gain is proposed. The interleaved structure is adopted in the low-voltage side of this converter to reduce the ripple of the current through the low-voltage side, and the series-connected structure is adopted in the high-voltage side to achieve the high step-up/step-down voltage gain. In addition, the bidirectional synchronous rectification operations are carried out without requiring any extra hardware, and the efficiency of the converter is improved. Furthermore, the operating principles, voltage and current stresses, and current ripple characteristics of the converter are analyzed. Finally, a 1 kW prototype has been developed which verifies a wide voltage-gain range of this converter between the variable low-voltage side (50–120 V) and the constant high-voltage side (400 V). The maximum efficiency of the converter is 95.21% in the step-up mode and 95.30% in the step-down mode. The experimental results also validate the feasibility and the effectiveness of the proposed topology.


I. INTRODUCTION
With the aggravation of the global energy crisis and the deterioration of the environment pollution, the renewable energy systems become very important in the world [1] , [2] . However, the renewable energy systems, including photo-voltaic systems and wind-power generating systems, cannot provide a stable power and supply enough instantaneous power when the load power suddenly increases. Energy storage systems, which are used to compensate the power fluctuation between the power generation side and the load side, play an important role in renewable energy power systems [3] , [4] . A bidirectional DC DC converter is a key device for interfacing an energy storage element such as a battery pack or a super-capacitor pack, with a DC bus [5] , [6] . The voltage of a storage battery is typically 48V or lower, while the voltage of a DC bus is 400V or higher [7] . Thus, a bidirectional DC DC converter with a wide voltage-gain range is desired for energy storage systems to connect a low-voltage battery with a high-voltage DC bus.
There are two different types of bidirectional DC-DC converters in different applications, which include the isolated converters and non-isolated converters. The isolated converters include the Flyback, the Forward-Flyback, the half-bridge and the full-bridge. High voltage-gain is obtained by adjusting the turns ratio of the high frequency transformer. However, the leakage inductance of the transformer results in high voltage spikes on semiconductors. In order to reduce the voltage stress caused by the leakage inductance, a full bridge bidirectional DC-DC converter with a Flyback snubber circuit [8] and a bidirectional DC-DC converter with an active clamp circuit [9] were proposed. Although the energy of the leakage inductor can be recycled, more additional circuits are required. Besides, when the input and the output voltages cannot match the turns ratio of the transformer, the switching loss will increase dramatically [10] .
The non-isolated converters include the Cuk, Sepic/Zeta, coupled-inductor, conventional buck-boost, three-level [11] - [14] , multi-level and switched-capacitor [15] . Due to the cascaded configurations of two power stages, conversion efficiencies of Cuk and Sepic/Zeta are lower [16] , [17] . Coupled-inductor converters can achieve a high voltage gain by adjusting the turns ratio of the coupled inductor [18] , but the problem associated with the leakage inductor is still difficult to be solved and the converter's power converting and transferring capabilities are limited by the capacity of the magnetic core. By utilizing a coupled-inductor, the Sepic converter has been modified, and a high efficiency and high voltage-gain bidirectional DC-DC converter with soft-switching was proposed in [19] . But it requires extra active power semiconductors and capacitors. Conventional buck-boost converters are good candidates for low-voltage applications due to its high efficiency and low cost. Unfortunately, the drawbacks including the narrow voltage conversion range, the high voltage stress and extreme duty cycles of semiconductors make them not suitable for energy storage applications. Though the conventional two-phase interleaved bidirectional DC-DC converter in [20] can reduce low-voltage side current ripples, but this converter still has disadvantages including the narrow voltage conversion range and the high voltage stress for power semiconductors. The voltage stress of power semiconductors of the bidirectional three-level DC-DC converters in [11] , [12] is half that of the conventional two-phase interleaved bidirectional DC-DC converter, but its voltage-gain range is still narrow. Besides, the low-voltage and high-voltage side grounds of this converter are connected by a power semiconductor, the potential difference between the two grounds is a high frequency PWM voltage, which may result in more maintenance issues and EMI problems. The low-voltage and high-voltage sides of the bidirectional three-level DC-DC converter in [14] share the common ground, but the voltage-gain of this converter is still limited. In addition, this converter requires the complicated control scheme to balance the flying-capacitor voltage. The converters in [13] , and [21] can achieve a high voltage gain, and the low voltage stress of power semiconductors. However, these converters need more power semiconductors, and require additional hardware circuits and control strategies to maintain the balanced voltage stress of power semiconductors. The switched-capacitor converter structures and control strategies are simple and easy to expand. Different charging and discharging paths of the capacitors transfer energy to either the low-voltage or the high-voltage side to achieve a high voltage gain. Single capacitor bidirectional switched-capacitor converters were proposed in [22] , [23] , but the converter efficiency is low. To reduce the input current ripple, interleaved switched-capacitor converters have been proposed in [24] - [27] . However, the converter in [24] needs more components, and the inductor currents of the converter in [25] are unbalanced when Db is not equal to 2Da. Although the bidirectional DC-DC converters in [26] , and [27] just need four semiconductors, the maximum voltage stress of the converter in [26] is that of the high voltage side, and the maximum voltage stress of the converter in [27] is higher than that of the high voltage side. The bidirectional converters in [28] , and [29] only require three semiconductors. But their voltage-gain ranges are still small. In addition, the low-voltage and high-voltage side grounds of these converter are connected by a power semiconductor or an inductor, which will also cause extra EMI problems. Finally, the high voltage-gain converter in [30] needs more power components and fails to achieve bidirectional power flows. In addition, the balanced inductor currents just can be achieved when the number of the voltage multiplier stages is odd. The converter in [31] suffers from the huge current ripple in the low-voltage side.
These non-isolated bidirectional DC-DC converters referred above cannot simultaneously achieve the low current ripple, the low voltage stress of power semiconductors and the wide voltage-gain range. In order to solve this problem, an interleaved switched-capacitor bidirectional DC-DC converter is proposed in this paper. Comparing with the conventional two-phase interleaved bidirectional DC-DC converter and the bidirectional three-level DC-DC converter, the proposed converter has advantages including low current ripple, low voltage-stress of power semiconductors and wide voltage-gain range. In addition, the connection between the low-voltage and the high-voltage side grounds of the proposed converter is a capacitor rather than a power semiconductor. To achieve a high step-up gain, the capacitors are charged in parallel and discharged in series in the step-up mode. Opposite to the step-up mode, the high step-down ratio can also be obtained because two capacitors are charged in series and discharged in parallel. Furthermore, the capacitor voltage of the proposed converter is half of the high-voltage side voltage, and the efficiency is improved by synchronous rectification operation. This paper is organized as follows. In Section II, the topology of the interleaved switched-capacitor bidirectional DC-DC converter is presented. In Section III, the operating principles of the proposed converter are analyzed in detail. The steady-state characteristics of the converter are analyzed in Section IV and experimental results are analyzed in Section V.

II. THE PROPOSED CONVERTER
The proposed interleaved switched-capacitor bidirectional DC-DC Converter is shown in Fig. 1. This converter is composed of four modules. Clow is the energy storage/filter capacitor of the low-voltage side. Module 1 includes power semiconductors Q1, Q2, and energy storage/filter inductors L1, L2. In addition, L1-Q1 and L2-Q2 form the parallel structure of the low-voltage side. Module 2 is a switched-capacitor network, including switched-capacitor units C1-Q3, C2-Q4 and C3-Q5. The interleaved structure is used in the low-voltage side of this converter. In this case, the duty cycles of Q1 and Q2 are the same, and the phase difference between the gate signals S1 and S2 is 180°. The low-voltage side, Module 1, Module 2 and the high-voltage side form the bidirectional DC-DC converter with the structure of the low-voltage-side in parallel and the high-voltage-side in series. Step-down Step-up

III. OPERATING PRINCIPLES
To simplify the steady-state characteristics analysis of the proposed converter, several reasonable assumptions about the operating conditions are made as follows: (a) all the power semiconductors and energy storage components of the converter are treated as ideal ones, and the converter operates in the continuous conduction mode (CCM); (b) all the capacitances are large enough that each capacitor voltage is considered as constant in each switching period.

A. Step-Up Mode
When the energy flows from the low-voltage side to the high-voltage side, the output voltage Uhigh is stepped up from Ulow by controlling the power semiconductors of Q1, and Q2, and the anti-parallel diodes of Q3, Q4 and Q5. The relationship between d1 and d2 can be written as d1=d2=dBoost, where d1 and d2 are the duty cycles of Q1 and Q2 respectively. Fig. 2 shows the typical waveforms in the step-up mode, and Fig. 3 shows the current flow path of the proposed converter.
Mode I: The power semiconductor Q1 is turned on and Q2 is turned off. The anti-parallel diode of Q3 is turned on, while the anti-parallel diodes of Q4 and Q5 are turned off. The current flow path of the proposed converter is illustrated in Fig. 3(a). The energy is transferred from the DC source Ulow to the inductor L1. Meantime, C1 is being charged by inductor L2, while C2 and C3 are discharging. C2 and C3 are connected in series to provide energy for the load in the high voltage side.
Mode II: The power semiconductors Q1 and Q2 are turned off. The anti-parallel diodes of Q3 and Q4 are turned on, while the anti-parallel diode of Q5 is turned off. The current flow path of the proposed converter is given in Fig. 3(b). Inductors L1 and L2 are discharging. Meantime, C1 is charging from inductor L2, while C3 is discharging. The DC source Ulow, L1 and C3 output energy to the load.
Mode III: The power semiconductor Q1 is turned off and Q2 is turned on. The anti-parallel diode of Q3 is turned off, while the anti-parallel diodes of Q4 and Q5 are turned on. The current flow path of the proposed converter is shown in Fig. 3(c). Inductor L1 is discharging, while L2 is charged by the DC source. Meantime, C3 is charged by C1, while C2 is charged by inductor L1. The DC source Ulow, L1 and C1 output energy to the load. Mode IV: Power semiconductors Q1 and Q2 are turned on. The anti-parallel diodes of Q3 and Q4 are turned off, while the anti-parallel diode of Q5 is turned on. The current flow path of the proposed converter is displayed in Fig. 3(d). Inductors L1 and L2 are charged by the DC source Ulow in parallel. Meantime, C1 and C2 are discharging in series to provide energy for the load.

B. Step-Down Mode
When energy flows from the high-voltage side to the low-voltage side, the output voltage Ulow is stepped down from Uhigh by controlling the power semiconductors Q3, Q4 and Q5, and the anti-parallel diodes of Q1 and Q2. The relationship between d3 and d4 can be written as d3=d4=dBuck, where d3 and d4 are the duty cycles of Q3 and Q4 respectively. Fig. 4 shows the typical waveforms in the step-down mode, and Fig. 5 shows the current flow path of the proposed converter.
Mode I: The power semiconductor Q3 is turned on, while Q4 and Q5 are turned off. The anti-parallel diode of Q1 is turned on, and the anti-parallel diode of Q2 is turned off. The current flow path of the proposed converter is shown in Fig. 5(a). C2 and C3 are charged by the DC source Uhigh in series. Meantime, inductors L1, L2 and C1 are discharging to provide energy for the load in the low voltage side.
Mode II: Power semiconductors Q3 and Q4 are turned on, while Q5 is turned off. The anti-parallel diodes of Q1 and Q2 are turned off. The current flow path is shown in Fig. 5(b). C1 is discharging to transfer energy to inductor L2, and simultaneously outputting energy to the load. Meantime, the DC source Uhigh charges L1 and C3, and simultaneously outputs energy to the load. In addition, C2 is discharging to supply energy to L1 and the load.
Mode III: The power semiconductor Q3 is turned off, while Q4 and Q5 are turned on. The anti-parallel diode of Q1 is turned off, and the anti-parallel diode of Q2 is turned on. The current flow path of the proposed converter is shown in Fig. 5(c). Inductor L2 is discharging to provide energy for the load. Meantime, the DC source Uhigh charges L1 and C1, and simultaneously provide energy for the load. In addition, C2 is discharging to supply energy to L1 and the load, and C3 is discharging to output energy to C1.
Mode IV: Power semiconductors Q3 and Q4 are turned off, while Q5 is turned on. The anti-parallel diodes of Q1 and Q2 are turned on. The current low path of the proposed converter is shown in Fig. 5(d). L1 and L2 are discharging to provide energy for the load in parallel. Meantime, the DC source Uhigh charges C1 and C2 in series, and C3 is discharging to supply energy to C1.   dBuck<1.

C. Synchronous rectification operation
without current with current during dead time As shown in Fig. 1, if the currents of the proposed interleaved switched-capacitor bidirectional converter flow into the corresponding anti-parallel diodes, it will result in the lower efficiency, as well as lower utilization of the power semiconductors. Therefore, a high step-up/step-down ratio switched-capacitor bidirectional DC-DC converter with synchronous rectification is proposed further in this paper.
The synchronous rectification operating principle of the switched-capacitor bidirectional converter is shown in Fig. 6. In the step-up mode, the main power semiconductors Q1 and Q2 switch according to gate signals S1 and S2 shown in Fig. 6(a). During the dead time td, the current has to fully flow into the corresponding anti-parallel diodes of Q3, Q4 and Q5. Otherwise, the current may flow into the controlled power semiconductors Q3, Q4 and Q5 due to their lower on-resistances and on-state voltage drops, as shown in Fig. 6(c), by means of the gate signals S3, S4 and S5 shown in Fig. 6(a). Similarly, in the step-down mode, the main power semiconductors Q3, Q4 and Q5 switch according to gate signals S3, S4 and S5 shown in Fig. 6(b). During the dead time td, the current also has to fully flow into the anti-parallel diodes of Q1 and Q2. Otherwise, according to the gate signals S1 and S2 shown in Fig. 6(b), the current flows into the controlled power semiconductors Q1 and Q2, as shown in Fig.  6(d).
Furthermore, the forward voltage drops of the anti-parallel diodes are close to zero. As a result, the controlled MOSFETs of the slave active power semiconductors can be turned on and turned off with ZVS, and the efficiency of the converter is further improved.

D. Control strategy of bidirectional power flow
Based on the operating principles above, the bidirectional power flow control strategy can be achieved as shown in Fig. 7. The voltages Uhigh and Ulow, and the current ilow are obtained by samplings. The interleaving structure is applied to reduce the current ripples. Similarly, the converter operates in the step-down mode when Uc=1, the voltage Ulow is controlled by the Buck voltage controller with the reference voltage Uref-Buck, and the feedback current ilow is controlled by the Buck current controller with the reference current Iref-Buck, which is in the opposite direction to the reference current Iref-Boost. The corresponding PWM schemes as shown in Fig. 4 and Fig. 6(b) are also selected to generate the gate signals S1~S5 in the step-down mode.

A. Voltage-gain in steady-state (1) Voltage-gain in step-up mode
As shown in Fig. 2(a) and Fig. 3(c), in the range of 0<dBoost<0.5, C1 and C3 are connected in parallel, so that the voltages of C1 and C3 are equal. According to Fig. 3(a)-(c) and the voltage-second balance principle on L1 and L2, the following equations can be obtained as Therefore, by simplifying (1), the following equations can be written as According to (2), the voltage-gain of the proposed converter in the step-up mode is 2/(1-dBoost), which is twice as big as the voltage-gain of the conventional interleaved bidirectional DC-DC converter. In addition, the voltage stress of C1, C2 and C3 can be reduced to half of the voltage Uhigh, and UC2, UC3 are self-balanced due to the switched-capacitor technique. Similarly, the corresponding voltage equations of the proposed converter within the range of 0.5 dBoost<1 can also be obtained, which are the same as those within the range of 0<dBoost<0.5.

(2) Voltage-gain in the step-down mode
As shown in Fig. 4(a) and Fig. 5(c), within the range of dBuck<1, C1 and C3 are connected in parallel, so that the voltages of C1 and C3 are still equal. According to Fig. 5(a)-(c) and the voltage-second balance principle on L1 and L2, the following equations can be obtained as Therefore, by simplifying (3), the following equations can be written as According to (4), the voltage-gain of the proposed converter in the step-down mode is dBuck/2, which is half of the voltage-gain of the conventional interleaved bidirectional DC-DC converter. In addition, the voltage stress of C1, C2 and C3 are still half of the voltage Uhigh, and UC2, UC3 are still self-balanced, which are the same as those in the step-up mode. Similarly, the voltage equations of the proposed converter within the range of dBuck<1 can also be obtained, which are the same as those within the range of 0<dBuck<0.5.

B. Inductor currents self-balance (1) Inductor currents self-balance in the step-up mode
According to Fig. 3(a)-(c), the currents of C1, C2 and C3 are as follows, within the duty cycle range 0<dBoost<0.5 in the step-up mode.
where IL1, IL2 and Ihigh are the average currents of iL1, iL2 and ihigh, and IC1, IC2 and IC3 are the average currents of iC1, iC2 and iC3 in the step-up mode respectively. In addition, '

C1
I is the average current of C1 when Q2 turns on. By applying the amp-second balance principle on capacitors C1, C2 and C3, the following equations (6)- (8)  In terms of (9), IL1 and IL2 are both half of the input current Ilow, i.e. the current self-balance is achieved in the step-up mode. Similarly, the corresponding current equations of the proposed converter within the duty cycle range 0.5 dBoost<1 can also be obtained, which are the same as those within the duty cycle range 0<dBoost<0.5.

(2) Inductor currents self-balance in the step-down mode
The currents of C1, C2 and C3 can be written as follows within the duty cycle range 0<dBuck<0.5, by means of Fig. 5(a) where IL1, IL2 and Ihigh are the average currents of iL1, iL2 and ihigh, and IC1, IC2 and IC3 are the average currents of iC1, iC2 and iC3 in the step-down mode respectively. In addition, '

C1
I is the average current of C1 when Q3 is turned off. By applying the amp-second balance principle on capacitors C1, C2 and C3, the following equations (11) By means of (14), IL1 and IL2 are also half of the input current Ilow, i.e. the current self-balance is also obtained in the step-down mode. In a similar way, the corresponding current equations of the proposed converter within the duty cycle range 0.5 dBuck<1 can also be obtained, which are the same as those within the duty cycle range 0<dBuck<0.5. Based on the analysis previously described, inductor currents self-balance can be achieved within the full duty cycle range for the proposed converter, in both step-up and step-down modes. This contributes to accurate current sensing, and eliminates an extra control loop that may require high performance circuits to balance phase currents.

C. Voltage and current stresses of power semiconductors (1) Voltage stress
As shown in Fig. 3(b, c) in the step-up mode and Fig. 5(b, c) in the step-down mode, power semiconductor Q1 is turned off and Q4 is turned on, so that Q1 and C2 are connected in parallel. Therefore the voltages of Q1 and C2 are equal. Similarly, the voltages of the other power semiconductors can also be obtained. According to (2) in the step-up mode and (4) in the step-down mode, the voltage stress for the power semiconductors can be written as follows Based on (15), all the voltage stresses of the power semiconductors and capacitors are half of the voltage Uhigh.

(2) Current stress
According to Fig. 3 and (9), the current stress of the power semiconductors in the step-up mode can be obtained by applying voltage-balance principle on C1, C2 and C3  (16) Similarly, according to Fig. 5 and (14), the current stress of the power semiconductors in the step-down mode can be obtained as (17 Based on (16) and (17), it can be seen that the current stress of Q2 is higher than that of Q1. But it is easier to choose a MOSFET with the high rated current rather than the one with the high rated voltage. Furthermore, the proposed bidirectional converter can obtain a high voltage gain while the duty cycle is in the range of 0.5<dBoost<1 in the step-up mode or 0<dBuck<0.5 in the step-down mode. Therefore, the difference of the current stress between Q1 and Q2 is limited, and it will not affect the selection of the power semiconductors.

D. Analysis of current ripples (1) Analysis of current ripples in the step-up mode
In the step-up mode within the range of 0<dBoost<0.5, it is assumed that L1=L2=L. According to Fig. 3 Where iL1, iL2 and ilow are the current ripples of iL1, iL2 and ilow. Similarly, the current ripples of iL1, iL2 and ilow within the range of 0.5 dBoost<1 can be described as follows

(2) Analysis of current ripples in the step-down mode
In the step-down mode within the range of 0<dBuck<0.5, it is also assumed that L1=L2=L. According to Fig. 5 Assuming that L1=L2=L fs=20kHz, Uhigh=400V, Ulow=50V~120V, and the rated output power Pn=1kW. The current ripple rate of iL1, iL2 and ilow is shown in Fig. 8, where i/I is defined as the current ripple rate. According to Fig. 8, the current ripple of the low-voltage side current ilow is smaller than those of iL1 and iL2 in both step-up and step-down modes. When Uhigh=400V and Ulow=50V~120V, the duty cycle varies in the range of 0.4<dBoost<0.75 in the step-up mode according to (2), and varies in the range of 0.25<dBuck<0.6 in the step-down mode in terms of (4). The current ripple rate of the low-voltage side current ilow is further reduced within the corresponding duty cycle range. Taking the step-up operating state as an example, when DC source is in the range of Ulow=50V~120V, the minimum ripple rate of the low-voltage side current is 0% when the duty cycle is dBoost dBoost<0.5, the maximum ripple rate of the low-voltage side current arrives at 27.4% when the duty cycle is dBoost=0. 4. In addition, the maximum current ripple rate of the low-voltage side arrives at 21.1% when the duty cycle is dBoost=0.67 within the range of 0.5<dBoost<0.75. Step up Step down Current Ripple rate i/I

Duty (d)
i low i L1 Fig. 8 The current ripple rate of iL1, iL2 and ilow.

E. Comparisons with other bidirectional solutions
According to the analysis above, the comparisons can be drawn among the proposed and the other bidirectional solutions in the step-up mode, as shown in Tab. 1. The bidirectional DC-DC converter in [14] only needs one inductor, but its ideal voltage-gain 1/(1-d) is limited due to the effects of parasitic resistance and extreme duty cycles. Although the voltage stress across the four semiconductors of this converter is half of the high-side voltage Uhigh, the current stress of the power semiconductors is rather high. In addition, this converter requires a complicate control scheme to balance the flying-capacitor voltage. The interleaved bidirectional DC-DC  [20] Ulow/(1-d) 4 2 Uhigh YES Converter in [25] 3Ulow/(1-d) 5 2 2Uhigh/3 When Db=2Da Converter in [26] 2Ulow/(1-d) 4 2 Uhigh YES Converter in [27] Ulow/(1-d) 2 [20] can reduce the current ripples in the low-voltage side, but it still has the disadvantages including the small voltage gain range and the high voltage stress across the power semiconductors. The interleaved bidirectional DC-DC converters in [25] - [27] have achieved a high voltage-gain, but the maximum voltage stress across the semiconductors of these converters are 2Uhigh/3, Uhigh and Uhigh+ Uhigh(1-d) respectively, rather than Uhigh/2, which will increase the switching losses and reduce the conversion efficiency. Besides, the converter in [27] can only achieve the inductor currents balance when the duty cycles are d=0.5, and the inductor currents of the converter in [25] are unbalanced when Db is not equal to 2Da. Regarding the proposed interleaved bidirectional DC-DC converter, the number of main components is equal to that of the converter in [25] , the voltage stress across all semiconductors and capacitors is Uhigh/2, and its voltage gain is higher than that in [14] and [20] . In addition, the inductor currents and the capacitor voltage self-balances can also be obtained within the full duty cycle range, in both step-up and step-down modes.

A. Small-signal modeling
It is assumed that the power semiconductors, the inductors, and the capacitors are all ideal. Then, the average model and the small-signal model can be obtained by using the state-space averaging method. According to Fig. 3(c)-(d) in the step-up mode (or Fig. 5(c)-(d) in the step-down mode), C1 and C3 are connected in parallel when Q2 and Q5 turn on, and Q3 turns off. It means the voltages across C1 and C3 are equal. So, there is an invalid state variable. By considering the equivalent series resistance (e.g. r=0.23 for C1), the coupling between the capacitors can be removed to avoid the invalid state variables.

(1) Small-signal modeling in the step-up mode
When the proposed bidirectional converter operates in the step-up mode in the range 0<dBoost<0.5, the main power semiconductors Q1 and Q2 have three effective switching states: S1S2=[10, 00, 01]. ulow(t), uhigh(t), and d1(t), d2(t) are the input variable, the output variable and the control variables respectively. iL1(t), iL2(t), uC1(t), uC2(t) and uC3(t) are the state variables. When S1S2=10, the converter operates in Mode I (as shown in Fig. 3(a)), and its operating time is d1(t) Ts. So, the state space average model can be obtained as follows where RL-Boost is the equivalent load resistance in the step-up mode. When S1S2=00, the converter is operating in Mode II (as shown in Fig. 3

(b)), and its operating time is [1-d1(t)-d2(t)] Ts.
The state space average model can be written as When S1S2=01, the converter operates in Mode III (as shown in Fig. 3(c)), and its operating time is d2(t) Ts. The state space average model can be achieved as Combining (22) and (23) with (24), the average model of the converter can be obtained as: In the duty cycle range 0.5<dBoost<1, the main power semiconductors Q1 and Q2 also have three effective switching states: S1S2= [10,11,01], and the converter is operating in Mode I, Mode IV and Mode III (as shown in Fig. 3). Their corresponding operating times are [1-d2(t

)]
Ts, [d1(t)+d2(t)-1] Ts and [1-d1(t)] Ts, respectively. Similarly, the corresponding average model of the proposed converter within the duty cycle range 0.5 dBoost<1 can also be obtained, which is the same as that within the duty cycle range 0<dBoost<0.5. Assuming that d1=d2=dBoost, the state variables, the input variable, the output variable and the control variable can be described by using the small-signal disturbance variables as: where IL1, IL2, UC1, UC2, UC3, Ulow, Uhigh and DBoost are the steady According to (27)

(2) Small-signal modeling in the step-down mode
When the proposed bidirectional converter operates in the step-down mode in the duty cycle range 0<dBuck<0.5, the main power semiconductors Q3, Q4 and Q5 have three effective switching states: S3S4S5=[100, 001, 011]. uhigh(t), ulow(t), and d3(t), d4(t), d5(t) are the input variable, the output variable and the control variables respectively. iL1(t), iL2(t), uC1(t), uC2(t) and uC3(t) are the state variables. In addition, C2 and C3 are connected in series, then connected with the DC source Uhigh in parallel. So, the equivalent series resistance (e.g. r1=0.1 for the DC source Uhigh) is considered to avoid the invalid state variables. When S3S4S5=100, the converter is operating in Mode I (as shown in Fig. 5(a)), and its operating time is d3(t) Ts. The state space average model can be obtained as follows L1 where RL-Buck is the equivalent load resistance in the step-down mode. When S3S4S5=011, the converter operates in Mode III (as shown in Fig. 5(c)), and its operating time is d4(t) Ts. So, the state space average model can be written as When S3S4S5=001, the converter is operating in Mode IV (as shown in Fig. 5(d)), and its operating time is Combining (29), and (30) with (31), the average model of the converter can be obtained as: In the duty cycle range 0.5<dBuck<1, the main power semiconductors Q3, Q4 and Q5 also have three effective switching states : S3S4S5=[100, 110, 011], the converter is operating in Mode I, Mode II and Mode III (as shown in Fig.

5), and their operating times are [1-d4(t)]
Ts, [d3(t)+d4(t)-1] Ts and [1-d3(t)] Ts, respectively. In a similar way, the corresponding average models of the proposed converter within the duty cycle range 0.5 dBuck<1 can also be obtained, which are the same as those within the duty cycle range 0<dBuck<0.5. Assuming that d3=d4=dBuck, the state variables, the input variable, the output variable and the control variables can be described by using the small-signal disturbance variables as: where IL1, IL2, UC1, UC2, UC3, Uhigh, Ulow and DBuck are the steady In terms of (34) and the experimental parameters in Tab. 2, when the output voltage is Ulow=50V, the control-to-output transfer function in the step-down mode can be achieved from the time domain to the complex frequency domain as

V. EXPERIMENTAL RESULTS AND AYALYSIS
In order to verify the feasibility of the proposed converter, a 1kW experimental prototype of the interleaved switched-capacitor bidirectional DC-DC converter is developed, which is shown in Fig. 9. The experiment parameters are shown in Tab. 2. Fig. 9 The experimental prototype of the interleaved switched-capacitor bidirectional DC-DC converter. Tab

A. Experimental results in the step-up mode
The voltage waveforms of the main and slave power semiconductors of the proposed converter in the step-up operation mode are shown in Fig. 10 and Fig. 11, respectively. The PWM voltage of each power semiconductors is 200V, namely half of Uhigh, which validates the analysis in Section IV. In addition, the current flows through the anti-parallel diodes of Q3, Q4 and Q5 during the dead time, and the blocking voltages of Q3, Q4 and Q5 are around zero. Otherwise, the controlled MOSFETs Q3, Q4 and Q5 are turned on and turned off with ZVS by the synchronous rectification, e.g. the gate signal S4 and the voltage stress of Q4 as shown in Fig. 11. When the input voltage is Ulow=50V, the output voltage Uhigh and the voltage across C3 are shown in Fig. 12. According to Fig.  12, the voltage across C3 is 200V (i.e. half of the output voltage). In addition, the potential difference between the input and output side grounds of this converter is just the voltage across C3 (i.e. the constant voltage 200V with very small ripple), rather than the PWM voltage.
The input and inductor currents of the proposed converter in the step-up operation mode are shown in Fig. 13. The inductor currents iL1 and iL2 are shown in Fig. 13(a). Fig. 13(b) shows the input current ilow and the inductor current iL1. According to Fig.  13, the current ripple rates of iL1 and iL2 are about 49%, and the current ripple rate of the input current is only 17.6%. According to (19), the ripple rate of iL1 and iL2 is 53.57%, and the current ripple rate of ilow is 17.86% theoretically, which agree with the experimental results. The conclusion that the current ripple of ilow is much lower than the current ripple of iL1 and iL2 can be obtained. The input and capacitor current waveforms of the proposed converter operating in the step-up mode are shown in Fig. 14, when the input voltage is Ulow=50V and the output voltage is Uhigh=400V. From Fig. 14, it can be observed that the amplitude of iC1 is higher than those of iC2 and iC3, and the maximum charge current of C1 is nearly equal to half of that of ilow. According to Fig. 3(a), the current flowing through Q3 is the charging current of C1. Thus, the conclusion that the current stress of Q3 is reduced to half of the input current can be obtained, which agrees with the theoretical analysis previously mentioned in (16). Besides, the average amplitude of the charging or the discharging current of C3 is the smallest one (less than 2A), which is conducive to reduce the voltage fluctuations between the input and output side grounds of this converter.
In the step-up mode, the output voltage can stay constant around the reference voltage 400V with the action of the voltage control loop. Fig. 15 illustrates the dynamical responses of the output voltage and the input voltage when the input voltage is changed from 120V to 50V continuously. According to Fig. 15, when the input voltage Ulow varies continuously from 120V to 50V, the output voltage still stays around 400V, which means the proposed converter can obtain a wide voltage-gain range varying from 3.3 to 8. Fig. 13 The input current ilow, inductor currents iL1 and iL2 when the input voltage is Ulow=50V and the output voltage is Uhigh=400V. (a) Inductor currents iL1 and iL2. (b) The input current ilow and the inductor current iL1. Fig. 14 The input current ilow, capacitor currents iC1, iC2 and iC3 in the step-up mode. (a) The input current ilow and the capacitor current iC1. (b) Capacitor currents iC2 and iC3. Fig. 15 The output voltage and the wide-range changed input voltage from 120V to 50V in the step-up mode.

B. Experimental results in the step-down mode
The voltage waveforms of the main and slave power semiconductors of the proposed converter in the step-down operation mode are shown in Fig. 16 and Fig. 17 respectively. Similar to the experimental results in the step-up mode, the PWM voltage of each power semiconductors is 200V, which is half of the high-voltage side Uhigh. In addition, the slave power semiconductors Q1 and Q2 are also turned on and turned off with ZVS in the synchronous rectification operation, and the gate signal S1 and the voltage stress of Q1 are shown in Fig. 17.
When the output voltage is Ulow=50V, the input voltage Uhigh and the voltage across C3 are shown in Fig. 18. According to Fig.  18, the voltage across C3 is also at constant 200V (i.e. half of the output voltage). In addition, the potential difference UC3 between the input and output side grounds of this converter also has a very small ripple and dv/dt, which is the same as that in the step-up mode. The output and inductor current waveforms of the proposed converter in the step-down operation mode are shown in Fig. 19. The inductor currents iL1 and iL2 are shown in Fig. 19(a). Fig.  19(b) shows the output current ilow and the inductor current iL1. According to Fig. 19, the current ripple rate of iL1 is 46%, and the current ripple rate of iL2 is 50.6%. In addition, the current ripple rate of the output current is 17.65%. According to (20), the ripple rate of iL1 and iL2 is 53.57%, and the ripple rate of ilow is 17.86% theoretically, which are in accordance with the experimental results. The conclusion that the current ripple of ilow is much lower than the current ripple of iL1 and iL2 can be obtained. Fig. 19 The output current ilow, inductor currents iL1 and iL2 when the output voltage is Ulow=50V and the input voltage is Uhigh=400V.   Fig. 20, it can be seen that the amplitude of iC1 is also higher than those of iC2 and iC3, and the maximum discharging current of C1 is also nearly equal to half of that of ilow. According to Fig. 5(a), the current flowing through Q3 is the discharging current of C1. Thus, the conclusion that the current stress of Q3 is also reduced to half of the output current can be achieved, which also agrees with the theoretical analysis previously mentioned in (17). Besides, the average amplitude of the charging or the discharging current of C3 is also the smallest one (less than 2A), which is the same as that in the step-up mode. Fig. 20 The output current ilow, capacitor currents iC1, iC2 and iC3 in the step-down mode. (a) The output current ilow and the capacitor current iC1. (b) Capacitor currents iC2 and iC3. Fig. 21 The input voltage and the wide-range changed output voltage from 50V to 120V in the step-down mode. Fig. 21 can be used to validate the converter s function of charging the super-capacitors or the batteries. According to Fig.  21, when the input voltage stays around 400V, the output voltage Ulow varies continuously from 50V to 120V under the control of the voltage loop (i.e. a PI controller), in which the reference voltage is adjusted from 50V to 120V over 10 seconds, while the input voltage keeps at 400V. Therefore, it means the proposed converter can obtain a wide voltage-gain range varying from 1/8 to 1/3.3, and it can charge the super-capacitors or the batteries in a wide terminal voltage range. Fig. 22 shows the hybrid energy sources storage system, where the super-capacitor bank adopts the super-capacitor of CSDWELL's model MODWJ001PM031Z2. In addition, the battery in the hybrid energy sources is a lithium iron phosphate battery with the rated voltage of 48V. The experimental results of the bidirectional power flow control are shown in Fig. 23.

C. Bidirectional power flow experiment
In the hybrid energy storage sources system shown in Fig. 22, Udc is the DC bus voltage, Ubat and Ibat are the output voltage and output current of the battery, Usc and Isc are the output voltage and output current of the super-capacitor, and Idc is the load current. In the experiment of the bidirectional power flow control, the output voltage of the battery is about 50V, the output voltage of the super-capacitor is around 40V, and the DC bus power varies with the step changes from 400W to 650W. The interleaved switched-capacitor bidirectional DC-DC converter proposed in this paper is applied to interface the super-capacitor and the DC bus, and it operates according to the control strategy shown in Fig. 7.

Battery Super Capacitor
Control system

Udc Idc
Boost converter

Proposed bidirection converter
Uc C + - Fig. 22 Hybrid energy sources storage system. Fig. 23 shows the variations of ibat and isc during the sudden increase and decrease in the loads of the proposed bidirectional converter, when super-capacitors are operating. According to Fig. 23, when the power required by the DC bus is changed from 400W to 650W with a step change, the control system sets the control signal Uc to "zero". At the same time, the proposed switched-capacitor bidirectional converter responds quickly and operates in the step-up mode. The current Isc increases from zero to 6A in 20ms approximately, and the instantaneous power provided by the super-capacitor is nearly equal to the required power change of the DC bus, avoiding the step change current from the battery, which may shorten the life of the battery. As a result, the current of the battery rises from 8A to 13A gradually, and the current of the super-capacitor falls to zero from Isc=6A. Similarly, when the power required by the DC bus is changed from 650W to 400W with a step change, the control system sets the control signal Uc to "1". At the same time, the proposed switched-capacitor bidirectional converter responds quickly and operates in the step-down mode. The current Isc increases from zero to 6A with the opposite direction in 20ms approximately. As a result, the current from the battery falls from 13A to 8A gradually, and the current of the super-capacitor falls to zero from Isc=-6A. Fig. 24 shows the variations of ibat and isc with the same load step change, when super-capacitors are not operating. According to Fig. 24, when the DC bus demand power is changed from 400W to 650W with a step change, the current Ibat quickly increases from 8A to 13A with a step change. When the DC bus demand power is changed from 650W to 400W with a step change, the current Ibat quickly decreases from 13A to 8A with a step change. It is seen that when the load power varies with a step change, the battery has to tolerate the step change current, and this is easy to cause the impact on the battery itself deceleration, and then shorten its service life.
Comparing the experimental results of Fig. 23 and Fig. 24, it is seen that when the DC bus demand power quickly increases or decreases, the proposed switched-capacitor bidirectional converter can respond quickly according to the control signal Uc, and the super-capacitor can compensate (take in and send out) the power gap between the battery and the DC bus side to ensure that the current output from the battery changes more slowly and therefore, avoid reduction of the battery life. The efficiencies of the proposed bidirectional DC-DC converter in the step-up and step-down modes are shown in Fig.  25 when the high-voltage side Uhigh is 400V and the low-voltage side Ulow varies from 50V to 120V or 120V to 50V continuously. The efficiencies are measured by the power analyzer YOKOGAWA/WT3000. According to Fig. 25, the measured efficiencies are from 91.88% (Ulow=50V) to 95.21% (Ulow=120V) in the step-up mode, and from 92.60% (Ulow=50V) to 95.30% (Ulow=120V) in the step-down mode. With the constant load Pn=1kW and Uhigh=400V in the step-up/down modes, the effective values of the low side currents increase due to the decrease of the low side voltages (i.e. the increase of the voltage-gain). Therefore, the turn-on/off losses, and the conduction losses of the power semiconductors will raise, as well as the conduction losses of the equivalent series resistors of the circuit. Moreover, the maximum efficiency arrives at 95.21% and 95.30% in the step-up and step-down modes respectively when the low-voltage side Ulow is 120V, and the efficiency in the step-down mode is slightly higher than that in the step-up mode.

VI. CONCLUSIONS
In this paper, an interleaved switched-capacitor bidirectional DC-DC converter has been introduced. The proposed topology can benefit from high step-up/step-down ratio, a wide voltage-gain range and avoiding of the extreme duty cycles. In addition, this converter has the advantages of the low voltage stress of power semiconductors and capacitors, and low current ripples in the low-voltage side. Besides, the slave active power semiconductors allow ZVS turn-on and turn-off, and the efficiency of the converter is improved. The capacitor voltages and the inductor currents can be easily balanced due to the self-balance function. The proposed bidirectional DC-DC converter has good dynamic and steady-state performance and is suitable for the power interface between the low-voltage battery pack and the high-voltage DC bus for various new energy storage systems.