Investigation of electrically active defects in InGaAs quantum wire intermediate-band solar cells using deep-level transient spectroscopy technique

InGaAs quantum wire (QWr) intermediate-band solar cell–based nanostructures grown by molecular beam epitaxy are studied. The electrical and interface properties of these solar cell devices, as determined by current–voltage (I–V) and capacitance–voltage (C-V) techniques, were found to change with temperature over a wide range of 20–340 K. The electron and hole traps present in these devices have been investigated using deep-level transient spectroscopy (DLTS). The DLTS results showed that the traps detected in the QWr-doped devices are directly or indirectly related to the insertion of the Si δ-layer used to dope the wires. In addition, in the QWr-doped devices, the decrease of the solar conversion efficiencies at low temperatures and the associated decrease of the integrated external quantum efficiency through InGaAs could be attributed to detected traps E1QWR_D, E2QWR_D, and E3QWR_D with activation energies of 0.0037, 0.0053, and 0.041 eV, respectively.


Introduction
In a photovoltaic semiconductor device, the inability to absorb light with energy less than the bandgap and the loss of photons with energies exceeding the bandgap as heat are considered to be the main fundamental effects that limit its efficiency [1]. Recently, the social interest in exploiting solar energy using the photovoltaic effect has led to a tremendous increase in the demand for solar cells. Therefore, it is essential to develop new technologies and concepts of producing solar cells in order to increase their efficiency. In 1961, William Shockley and Hans Queisser calculated the maximum theoretical efficiency limit of p-n junction-based photovoltaic solar cells to be 30% for an optimised semiconductor bandgap of 1.1 eV. This limit is known as Shockley-Queisser limit or the detailed balance limit of efficiency [2]. This formalism has been used by many authors to model solar cells [1]. Consequently, different approaches have been proposed and attempted in order to increase the efficiency of solar cells above that limit. Tandem, multiband, hot carrier, intermediate level, impurity level, and quantum well solar cells are good examples of these approaches [3].
In 1997, Luque et al [4] theoretically predicted that intermediate-band solar cells (IBSCs) could increase the efficiency of solar cells up to 63.1% under maximum concentrated sunlight. The main principle of these cells is to introduce one or more electronic bands (called intermediate bands or levels) inside the main bandgap of a conventional semiconductor [6,7]. Hence, the IBSCs are expected to have an increase in photocurrent [5] without voltage degradation [6].
The fabrication and investigation of IBSC-based devices has received considerable interest worldwide because of the relevance of these devices to enhanced-efficiency solar cells [7]. Specifically, the three main approaches adopted to fabricate an IBSC are: (i) use of quantum dot technology as a way of engineering the IB material, (ii) direct synthesis of the IB material, and (iii) formation of a localized absorber layer within a highly porous, large bandgap semiconductor [8]. However, amongst these three methods, the quantum dot (QD) technology is the most promising technique for realizing the IB idea and studying its principle of operation [6]. In this technique, a QD structure is inserted between the bandgap of the conventional semiconductor so that charge carriers are quantum confined in three directions. Consequently, this allows QDs, which have a discrete delta-like density of states, to create the required intermediate band that has a separate quasi-Fermi level from the conduction and valence band of the semiconductor [9]. However, the incorporation of QDs leads to a reduction of the photoelectrical conversion efficiency (PCE) of QD IBSC due to the formation of strain and resulting dislocations, which lead to the deterioration of the open-circuit voltage, V oc [6,10,11]. To increase the PCE of QD IBSC, insertion of δ dopants into the QDs was proposed [12,13]. By using n-type δ dopants, the electron intersubband QD transitions will be increased, the recombination losses through QDs will be decreased as a result of the reduction of electron capture processes, and the deterioration of V oc will be inhibited. Hence, this will enhance the infrared absorption and the photocurrent in QD IBSC [12,13].
Kunets et al [7,14] used the just-discussed principle to fabricate an IBSC device consisting of a one-dimensional InGaAs quantum wire (QWR) structure instead of using zerodimensional QDs or two-dimensional quantum wells (QWs). The QWRs were inserted into a GaAs p-i-n junction. The QWR structure has a good configuration that allows the device to have more efficient light absorption compared to zero-dimensional systems [13]. Moreover, photocurrent can be generated in the plane of the QWRs [15,16]. In addition, QWRs are expected to have applicable lifetime of photogenerated carriers [16]. Kunets et al [7,14] also studied the effects of n-type Si delta doping on the external efficiency of this QWRs-based IB solar cell structure. They observed that, at room temperature, the solar energy conversion efficiencies of the reference p-n junction and p-i-n solar cell samples were 4.1 and 4.5%, respectively, whereas samples with incorporated QWRs and delta doping showed an increase of efficiency up to 5.1% and 5%, respectively. However, they reported that the short circuit current increases and causes a comparatively lower open circuit voltage V oc (20-50 mV), which results in a severe degradation of the performance of the solar cell.
In this work, a detailed investigation is carried out on electrically active defects in a set of (311)A GaAs solar cell structures gown by molecular beam epitaxy (MBE) [7,14]. The devices investigated are p-n (labelled PN, first reference sample), p-i-n (labelled PIN, second reference sample), undoped p-i-n with InGaAs quantum wires (labelled QWR undoped) and Si δ-doped p-i-n with InGaAs quantum wires (labelled QWR doped). This study will help form a better understanding of the physical phenomena that affect the efficiency of these solar cell structures using current-voltage (I-V), capacitance-voltage (C-V), conventional DLTS, and Laplace DLTS characterisation techniques.

Sample details
The details of sample growth are given elsewhere [7]. In summary, a solid-source MBE 32P Riber system was used to grow the devices on semi-insulating (311)A GaAs substrates. It is well known that the high index (311)A plane is a good template for the growth of QWRs. Also in this plane, a strong built-in piezoelectric field can be generated in the presence of strain [17]. The first GaAs PN reference device (SE159) consisted of a 400 nm GaAs buffer layer grown at a growth temperature of 580°C. Then the growth temperature was decreased to 540°C and a 1 μm thick GaAs layer doped with Si was grown with high V/III flux ratio (V/III=20). This low growth temperature and high V/III flux ratio make the GaAs layer achieve a high n-type doping efficiency on the (311)A surface. This was followed by a 1 μm thick p-type GaAs layer doped with Si grown at a higher growth temperature (580°C) and low V/III flux ratio (V/III=7) to achieve p-type conductivity. The second reference device (PIN device, SE164), which was grown using the same growth conditions and consisted of the same layers as the PN device, has an additional 330 nm thick GaAs intrinsic region grown at 540°C and is sandwiched between the p and n layers. The third device (QWR undoped device, SE160) was grown by incorporating an intermediate band in the GaAs i-region without any intentional doping. The i-region consisted of 10 periods of 11 monolayers of In 0.4 Ga 0.6 As QWRs separated by 30 nm GaAs barriers. The InGaAs quantum wires were grown at 540°C. Finally, the fourth device (QWR doped, SE162) is similar to the third device structure, but in the middle of each 30 nm thick GaAs barrier, a Si n-type δdoping with a sheet concentration N 2D =1×10 11 cm −2 was inserted. In each of these structures, the doping concentration of the n-type and p-type GaAs layers was 5×10 17 cm −3 and 1×10 17 cm −3 , respectively. The samples were processed in circular mesas having diameters of 900, 400, 549, and 400 μm for PN, PIN, QWR undoped, and QWR doped devices, respectively. These mesas were formed by wet chemical etching down to the n-type GaAs contact layer, and 75 nm AuGe/15 nm Ni/ 200 nm Au was deposited to form an O-ring-shaped n-type contact. The top circular mesa p-type contact consisted of 100 nm AuZn/200 nm Au. The n and p contacts were annealed at 420°C for 2 min and 350°C for 30 s, respectively, using rapid thermal annealing technique. The schematic diagrams of the solar cell devices investigated in this study are shown in figure 1.   orders of magnitude when compared to the reference PN devices. However, the QWR doped samples have the highest dark current density at all reverse bias voltages amongst all devices. The decrease or increase in the leakage current, which could be attributed to a decrease or increase of the number of defects and their concentrations, will be further investigated using DLTS experiments. Furthermore, the QWR undoped devices have the lowest forward current density as compared to all the other devices. However, Lu et al [18] reported an increase of the forward current density at 310 K when incorporating In 0.5 Ga 0.5 As QDs to GaAs p-i-n solar cells grown on n + GaAs (001) substrates by metal organic chemical vapour deposition. They related this behaviour to the creation of additional recombination paths via QD states as a result of the presence of QDs in the depletion region. Moreover, it can be seen from figure 2(b) that the QWR undoped devices have a turn-on voltage (V on ) of 0.77 V, which is higher than the V on of the PIN devices (V on ∼0.68 V). This behaviour can be explained by the creation of new defect states in the undoped i-region where the QWRs are incorporated. However, the QWR doped samples have the lowest V on at around 0.51 V, while the reference PN devices have V on at around 0.57 V.

Results and discussion
In order to get more insight into the functioning of the pi-n devices, dark J-V measurements were carried out for all devices as a function of temperature (20-340 K at 20 K intervals); however, for clarity purposes, only selected presentative curves (20-320 K at 40 K intervals) are shown in figure 3. The steady increase in the forward dark current with temperature for PIN devices (see figure 3(b)) is normally attributed to the exponential change of the concentration of the intrinsic carrier, n i , in the depletion region with temperature [19]. The forward-biased dark current density transport characteristics of the QWR undoped devices have more pronounced temperature dependence as compared to the reference devices (i.e., PN and PIN), while the forward dark current density for the QWR doped devices have less noticeable temperature dependence as compared to the PIN and QWR undoped devices.
Additionally, at low temperatures, the QWR undoped devices exhibit an oscillation in the forward dark currents (see figure 4 for a temperature of 20 K). The same behaviour was also observed at low temperatures (T<70 K) by Lu et al [18] in QD-based solar cell devices. They suggested that these complicated dark current behaviours need to be interpreted by developing a new physical model for QD solar cells rather than using the conventional diode model. In contrast, the forward dark current of the QWR doped devices follows a trend similar to that of the reference PN device.
Normally, the forward bias dark current is produced in a standard p-i-n solar cell via two mechanisms, namely, recombination current in the space charge region (SCR) and diffusion current through the SCR. Moreover, the change in the shape of the dark J-V curves as a function of temperature depends on the temperature dependence of the concentration and carrier capture cross-sections of different types of defects, as well as tunneling effects [20]. Besides, for the QWR devices, there are additional recombination paths that are created via QWR states and subsequently they will contribute to the dark current. The carrier capture and recombination processes under different voltage biases and temperatures are the main parameters that control the amount of additional dark current.
The J-V characteristics for all devices are analysed further to understand their properties by calculating the local ideality factor, n(V), using the following approximated equation [18,21]: where V t is the thermal voltage. V t is given by V t =k B T/q. The local ideality factors for all devices are calculated at room temperature and their values change with voltage as shown in figure 5. Three different regions generally appear around 0.2, 0.4, and 0.5 V, indicating that the currents transition between different dominating mechanisms [18,21] in the devices. The n(V) behaviour over certain voltage ranges is similar for all devices. However, the QWR devices have unique trends at other voltage ranges. This suggests that some mechanisms are presumably enhanced or suppressed after adding QWRs, and some of the mechanisms are possibly unique to the QWR devices. It is worth pointing out that these results are in good agreement with the previous study carried out by Kunets et al [7] for the same devices.
To gain better understanding of the different conduction mechanisms occurring in the investigated devices, the local ideality factor versus voltage at different temperatures was   determined for all devices, as illustrated in figure S1 (see supplementary information). As can be seen, for each device, there are two noticeable behaviours observed in low-voltage and high-voltage regions. In particular, at low voltages, all devices exhibit a clear peak. However, for the QWR devices, this peak becomes more significant (n?1) as the temperature decreases and it shifts to higher voltages. Conversely, for PN and PIN devices, this low-voltage peak is almost temperature independent and has a very small amplitude as compared to the QWR devices, where n is much greater than unity. It is well known that tunnelling or generation/recombination processes can account for large ideality factors (n>1) [22]. These processes could also explain the large ideality factors observed in samples that incorporate QWRs in the intrinsic region and which create an additional current component that contributes to the total current of the devices. Thus, the trend of the ideality factor at low voltages provides evidence of enhanced recombination via QWRs in these devices. A similar behaviour has been reported in QD-based solar cell devices [13]. Furthermore, for QWR-doped samples, as a result of n-type Si δ-doping, the electrons will easily occupy the QWRs, and this leads to a strong local potential barrier around the QWRs. Thus, the electron mobility in the conduction band can be reduced as a result of variations of the local potential around the QWRs [11]. As a result, the J-V characteristics of these devices are worsened as evidenced by their larger ideality factors. It is worth pointing out that a similar behaviour of the local ideality factor at low voltage biases was observed by Gu et al [21] in InAs/InGaAs quantum dots-in-a-well solar cells and by Kim et al [23] in InAs QD solar cells. As can be seen in figure S1 (see supplementary information), at higher voltages, the local ideality factor increases approximatively linearly with bias for all devices. These large values normally reflect that the series resistance effect becomes predominant [18,21]. According to the obtained data, the local ideality factor of the PIN and QWR undoped devices is temperature dependent but the rate of change with the temperature is faster for the undoped QWR devices. However, for the PN and doped QWR devices, the local ideality factor is practically temperature independent. Figure 6 displays the first derivative of the J-V characteristics of all devices at temperatures 200 K. For clarity purposes, the first derivative of the J-V characteristics of all devices is replotted at 260 K, as shown in the inset of figure 6(d). A negative differential resistance (NDR) region is only noticeable in PIN and QWR undoped devices at temperatures above 200 K and under higher forward bias regime. The appearance of the NDR is presumably due to the resonant tunnelling of electrons (or holes) through the quasi-bound levels in the QWR region [23,24]. Clearly, figure 6(c) shows the increase of the peak-to-valley ratio as the temperature increases while, when the temperature was reduced, no NDR region was observed. Houng et al [25] attributed the NDR behaviour at room temperature to the resonant interband tunnelling (RIT) effect. The disappearance of the NDR at low temperatures is suggested to be due to the effect of bandgap widening at low temperatures [25]. Thus, in PIN and QWR undoped devices, the carriers are thermally activated to the allowed bands from which they can tunnel. Therefore, at low temperatures a few carriers are available in the band, hindering the observation of resonant tunnelling, as shown in figures 6(b) and (c). Additionally, the thickness of the deltadoped layer is an important parameter of device design, having a direct influence on whether RIT occurs or not [25]. Indeed, as can be seen in figure 6(d), when the delta-doped layer is incorporated in the QWR devices, the NDR behaviour disappears.

C-V characteristics
In order to determine the apparent free carrier concentrations and to have specific understanding of the junction structure of these devices, capacitance-voltage (C-V) measurements have been performed at a frequency of 1 MHz. Figure 7 depicts the dependence of the capacitance/area (C/A) as a function of bias voltage recorded at temperatures 300 and 20 K for all devices. In the p-n devices investigated in this work, a maximum room temperature capacitance, C max , is observed in forward biases as shown in figure 7(a). C max increases in the following sequence: C max1 (PN)<C max2 (PIN)<C max3 (QWR undoped)<C max4 (QWR doped). The same behaviours were also observed by Gunawan at al [26] in p-n wire-array solar cells with different microsphere diameters fabricated by lithography technique. They observed an increase of C max as the wire diameter increased. They suggested that this increase of C max was due to the extra cylindrical sheath surface of the wires. It is worth pointing out that in the devices investigated by Gunawan at al [26] the wires were vertical, while in this study the devices incorporated lateral wires (QWRs).
As the structure of the devices investigated are p-i-n junctions, the capacitance is expressed by the following equation: where d represents the thickness of the intrinsic region (cm), x n,p is the depletion region in both n and p sides (cm), respectively, and ε s is the permittivity (F·cm −1 ) of GaAs (12.9 ε 0 [22]) . As the doping levels of the n and p layers are fairly high, it is very likely that the intrinsic region dominates the overall capacitance because d is considered to be?x n,p . Consequently, the capacitance should vary only slightly with bias in reverse conditions. As shown in figure 7, the capacitance change as function of reverse bias in PIN and QWR undoped devices is very slow as expected by equation (1). However, for the QWR doped samples, this behaviour deviates considerably from the one described by equation (1) and it follows the same trend as the PN devices. The reason is very likely due to the effect of introducing n-type Si δ-doping, which makes the QWR doped junction behave as a PN junction.  Figure 7(b) shows that the capacitance/area at T=20 K decreases with increasing reverse bias, a behaviour which is frequently observed in this kind of device due to the increase of the depletion layer width. However, the most interesting features observed in the C-V characteristics are the plateaux or multiple steps detected in the QWR samples. For the QWR undoped devices, the plateau appears only in the forward bias (0.24-1.0 V), while the steps are present in the QWR doped devices over the whole bias range. The distinct behaviours of the capacitance in QWR undoped devices can be related to a two-dimensional electron gas (2DEG) formation as a result of electron localisation in the InGaAs wetting layer (WL). Chiquito et al [27] observed a plateau-like dependence in their C-V measurements at the bias range 0.5 to 1.5 V in an InAs/ GaAs self-assembled QD system. They related this behaviour to the formation of 2DEG at the (GaAs) 4 /(AlAs) 11 /GaAs top interface rather than at the WL because their PL and Raman scattering measurements proved that there was no contribution of the WL. In fact, the capacitance increase and the plateau features that are observed in the capacitance measurements for a bias range of 0.24-1.0 V, as shown in figure 7(b) for QWR undoped samples, could be attributed to the confinement of electrons at the InGaAs WL. Recent photoluminescence (PL) measurements performed by Kunets et al [7] provided strong evidence of the contribution of the WL in QWR devices. Therefore, one could conclude that a 2DEG is created in the InGaAs WL when a forward bias is applied in the QWR undoped devices investigated here and would account for the plateaux observed in the C-V characteristics. When a sufficiently high forward voltage is applied, the capacitance decreases, as shown in figure 7(b), because the 2DEG layer is fully depleted of electrons. Babinski et al [28] reported a similar behaviour at V=0.7 V in In 0.6 Ga 0.4 As/GaAs QDs grown by metalorganic vapour phase epitaxy. They explained the plateaux formation in the forward bias voltage by the QD excited states being filled by electrons or a DEG formed in InGaAs WL. It is, however, worthwhile mentioning that Kim et al [29] observed a hump shape at a forward voltage near 0.4 V in InAs/GaAs QD Schottky diodes grown by MBE; they related this hump to the carrier accumulation in the QD layer.
In order to investigate further the behaviour of C-V characteristics, C-V measurements were performed at low frequencies for both doped and undoped QWR devices. The apparent carrier concentration profile as function of depth is also calculated by using the following relations [30]: , where W is the length of the depletion region and N W CV ( ) is the apparent carrier concentration for semiconductors with quantum confinement [31]. Figure S2 (see supplementary information) shows the C-V and N CV of doped and undoped QWR devices at 100 K at low and high frequency. It can be seen from the C-V plots that there is no significant capacitance difference between the C-V measurements at low and high frequency. Similarly, the N CV plot at both frequencies in undoped and doped samples is unchanged. The C-V and N CV have no frequency dependence, which confirms that the emission of electrons from quantum wires is very fast.
In order to determine the distance between the steps observed in figure 7(b) for the QWR devices, the derivative of capacitance (dC/dV) was calculated, as shown in figure 8. One could approximate the number of charge carriers accumulated in the QWR doped layers by using Q=C p ΔV, where C p represents the capacitance at the plateau and ΔV represents the width of the plateau region [32]. The accumulation charge in the first, second, third, fourth, and fifth QWR layers of the QWR doped samples are calculated to be Q 1 =4.02×10 −11 C, Q 2 =4.72×10 −11 C, Q 3 =4.73× 10 −11 C, Q 4 =4.94×10 −11 C, and Q 5 =5.43×10 −11 C, respectively. These values are associated with the fact that, as the step is wider, the carrier concentration confined in the QWR layer is higher [33,34]. For the undoped QWR devices, there is only one accumulation layer with a charge Q=8.56×10 −11 C. As shown in figure 8, for the QWR doped samples, the width of the steps (ΔV) increases as the reverse bias increases. This increase could be attributed to the increase of the electrical field in the space charge region [35,36]. Because of this, for small reverse biases, the first QWR layer is depleted of electrons while all the other QWR layers in the device remain electrically neutral. When the reverse voltage is increased further, the conduction electrons are depleted to the second QWR layer, and therefore the boundary of the space charge region moves to the second QWR. This process will carry on until all the QWRs are depleted. Thus, the number of steps in the capacitance curve is related to the number of depleted QWR layers in the device.

DLTS and Laplace DLTS characteristics
In order to explore the effect of the electrically active defects on the solar cell efficiency in GaAs (311)A solar cell devices, DLTS experiments [37] were carried out at basing conditions of a reverse bias V R =−0.25 V, with filling pulse height V P =0 V and filling pulse duration t p =1 msec. The sample temperatures were scanned from 10 K up to 450 K. Figure 9 shows normalized DLTS spectra for all devices. DLTS measurements reveal a distinct broad minority electron trap peak (negative peak) over a wide range of temperatures in all devices which can be resolved by Laplace DLTS measurements [38]. In PN devices, in addition to the broad electron peak, a hole trap is also detected (positive peak).
Laplace DLTS was used in order to resolve the broad electron trap peak detected in all samples. Figure 10 shows that the broad DLTS peak observed for QWR doped devices over the temperature range ∼14-144 K (see figure 9) splits into three clear peaks, as detected by the high-resolution Laplace DLTS at T=53 K. In summary, the Laplace DLTS revealed the presence of the following traps: (i) PN: three electron traps (E1 PN to E3 PN ) and one hole trap (H1 PN ); (ii) PIN: two electron traps (E1 PIN & E2 PIN ); (iii) QWR undoped: three electron traps (E1 QWR to E3 QWR ); (iv) QWR doped: three electron traps (E1 QWR_D to E3 QWR_D ).
The Arrhenius plots of the emission rates as a function of temperature (ln (e n /T 2 ) versus (1000/T)) for each defect level detected by Laplace DLTS are shown in figure S3 (see supplementary information). The trap activation energies and capture cross-sections are calculated from the slope and intercept of these plots, respectively. These are summarized in table 1 with the concentrations of each trap. It is worth mentioning that the trap concentrations are calculated from the peaks of Laplace DLTS signal and C-V measurements.
As seen in table 1, only one hole trap, H1 PN , is detected in PN devices. It has an energy close to that measured from Laplace DLTS by Boumaraf et al [39] in a p-type Si-doped GaAs Schottky diode. Although the origin of this defect is not yet clear, they suggested that it could be related to complexes involving silicon atoms, background impurities, and defects originating from the growth conditions used. E1 PN has an activation energy comparable to the trap reported in GaAs [40]. However, the origin of E1 PN is still not known.
It can be seen from table 1 that the shallow trap E2 PN in the PN reference device has approximately the same activation energy as trap E3 QWR_D detected in the QWR doped devices, and could possibly originate from the same defect. This trap might be assigned to an arsenic vacancy v As introduced in electron-irradiated GaAs (labelled E 1 ) and whose activation energy was found to be 32-45 meV [41][42][43][44] below the conduction band. It is worth pointing out that this is the only trap that is common in the QWR doped and PN devices. In the earlier analysis of the C-V characteristics, it was concluded that the QWR doped junction acts as PN junction as a result of introducing n-type Si δ-doping. This common shallow trap might justify this assumption in C-V. However, the capture cross-section and concentration of this trap in QWR doped devices are higher than those of the PN devices. According to the previous study [7] for this QWR doped device, the fitting of PL spectra at a high excitation intensity of 3000 W cm −2 shows an energy difference between the wires and the 2D wetting layer transition to be 46 meV. This energy difference is nearly equal to the trap E3 QWR_D activation energy. Thus, there is another possibility that E3 QWR_D could be related to the inter-band energy transition between the InGaAs wire and the 2D WL where tunnelling to the conduction band could occur. E3 PN trap with an activation energy of ∼0.095 eV can be related to the well-known  electron trap in GaAs grown by MBE, M0 (E c -0.10 eV), that originated from chemical impurities during growth [45].
It can be seen from table 1 that the electron traps E1 PIN and E2 PIN in the PIN devices have similar activation energies as the electron traps E2 QWR and E3 QWR in the QWR undoped devices, respectively. These traps in both PIN and QWR undoped devices may originate from the intrinsic GaAs region since these were not observed in PN devices. One can therefore infer that, by introducing n-type Si δ-doping in QWR doped samples, E2 QWR and E3 QWR traps were annihilated. Additionally, it is found that the trap densities and apparent capture cross-sections of E1 PIN and E2 PIN are affected by the introduction of the InGaAs QWRs intermediate band. From DLTS measurements, Lee et al [46] detected an electron trap with activation energy of 0.14 eV in InAs/GaAs δ-doped QD solar cell structures grown by MBE and they identified this trap to M1 defect, which is commonly observed in GaAs layers grown by MBE [45]. Furthermore, E2 PIN and E3 QWR have comparable activation energies as trap F (0.14 eV) reported by Asano et al [47] in GaAs (001)/ InAs/InGaAs/GaAs self-assembled QD structures. In their study, they inferred that the increase of the density of this trap and other traps around the QDs is due to the growth conditions of InGaAs/GaAs QD structures. In particular, the density of these defects were reduced by a factor of 20 when they used migration-enhanced epitaxy to grow the GaAs capping layer at 400 or 500°C as compared to using MBE for a growth temperature of 500°C. Also, Fang et al [34] detected the M1 defect in In 0.5 Ga 0.5 As/GaAs QDs structures grown by MBE and they attributed this defect to point defects instead of defect-impurity complexes. Moreover, Kunets et al [48] observed the M1 trap in In 0.35 Ga 0.65 As/GaAs QD structures grown by MBE using noise spectroscopy measurements, and they related the increase of its density in the vicinity of In 0.35 Ga 0.65 As QDs to strain. Thus there is a consensus that E2 PIN and E3 QWR are related to M1 defect, which could be assigned to defect-impurity complexes or/and point defects [34,45,48,49]. The shallow trap E1 QWR with energy of ∼10 meV is only observed in QWR undoped devices. Thus, in this work it is believed that the E1 QWR level is created due to the incorporation of InGaAs QWRs. From a rectangular potential well calculation using the Nextnano software, Vakulenko et al [50] found that the quantum energy of the ground state in InGaAs/GaAs QD structures is approximately 10 meV. This finding provides further evidence that the E1 QWR trap could be related to the incorporation of the QWRs.
For QWR doped devices, the traps E1 QWR_D to E3 QWR_D are directly or indirectly related to the introduction of the n-type Si δ-doping since these traps were not observed in PIN and QWR undoped devices. The shallow trap E2 QWR_D has an activation energy of ∼5.3 meV, which is comparable to the ionization energy of silicon donors in GaAs (5.8 meV) [51]. Furthermore, Teh et al [52] found a similar trap level with concentration ∼10 15 cm −3 using the temperature dependence of the double exponential decay measurements. They assigned this trap to silicon substituting for a gallium centre, Si Ga , with binding energy of 5.85 meV. It is relevant to note that some of the traps detected in the devices investigated in this work are reported here for the first time. Their origins are not clear and further investigations are needed.
These DLTS measurements for PIN, QWR undoped, and QWR doped devices are correlated with the earlier solar conversion efficiency measurements done by Kunets et al [14] at different temperatures (83-300 K). In their measurements, they found that the efficiency increases as the temperature decreases in all devices until the temperature reached down to between 180 and 160 K, where the trend changed. In particular, in the PIN devices, the efficiency showed very small increments as the temperature decreased while, for the QWR undoped samples, the efficiency increased considerably as the temperature decreased down to ∼120 K and then the efficiency decreased for lower temperatures. For the QWR doped devices, the efficiency tended to decrease as the temperature decreased. The dramatic changes in the efficiency in the temperature range below 160-180 K can be correlated to the peaks observed in the DLTS spectra over the same temperature ranges (see figure 9). Moreover, this analysis of the DLTS and Laplace DLTS spectra demonstrates as well a reasonable correlation with the external quantum efficiency (EQE) study done by Kunets et al [14] on these devices at different temperatures. In their work, they correlated the lower solar conversion efficiency values in the QWR undoped devices (compared to the PIN and QWR doped samples in the temperature range 160-240 K) to their lower integrated EQE over the same temperature. This behaviour has been explained by measuring the GaAs EQE. The integrated GaAs EQE measurements showed an obvious U-shape trend as a function of temperature for QWR undoped devices; however, for the reference PIN devices, the GaAs EQE characteristics were almost temperature independent. In this study [14], this behaviour can be associated with the electrically active traps E2 QWR and E3 QWR since they were detected within the temperature ranges where the solar conversion efficiencies were low. Although the PIN and QWR undoped devices have similar defects in terms of activation energy, the capture cross-sections of the QWR undoped devices are higher. Therefore, these higher cross-sections of these defects could have more influence on the solar conversion efficiencies. However, a rapid increase of solar conversion efficiency and associated increase of the integrated EQE signal at low temperatures (T<∼120 K) observed in InGaAs QWR undoped devices could be attributed to the incorporation of QWRs, which introduce an intermediate energy band for enhanced energy harvesting and therefore enhanced efficiency. This level/band, E1 QWR , was indeed detected by DLTS in the InGaAs QWR undoped samples. In the QWR doped devices, however, it was reported that the solar conversion efficiencies and integrated InGaAs EQE decrease at low temperatures (T<∼120 K). This behaviour could be attributed to the three traps E1 QWR_D to E3 QWR_D detected by DLTS. E2 QWR_D has an energy comparable to the ionisation energy of Si as discussed previously. E1 QWR_D and E3 QWR_D , which were not observed in the PIN or QWR undoped samples, could be also assigned to complexes involving Si atoms via delta-doping.

Conclusion
I-V, C-V, DLTS, and Laplace DLTS techniques were used to investigate the existence of defects in GaAs p-i-n solar cells incorporating undoped and doped intermediate-band QWRs in the intrinsic region of the device junction. Analysis of the J-V dependence showed that the QWRscontaining devices exhibited a clear peak of the local ideality factor at small forward biases at all temperature conditions, which might be caused by the charges captured at the QDinduced defect states. Under large forward biases, meanwhile, the temperature dependence of the ideality factor for all devices was well related to the effect of the series resistance. In addition, the C-V measurements at T=20 K revealed plateaux in QWR undoped devices which were related to 2DEG or/and the carrier accumulation in the QD layer; for the QWR doped devices, the ith steps observed in the C-V plots were related to the depletion of the ith QWR in the devices. The efficiency and EQE characteristics obtained by Kunets et al [14] at different temperatures correlated with the appearance of trap peaks observed in the DLTS and Laplace DLTS spectra at almost the same temperature ranges. An IB level/band with energy of ∼10 meV detected by Laplace DLTS in QWR undoped devices was related to the ground state energy of InGaAs QWRs. From these results, it is concluded that the observed defects play an important role in the efficiency of QWRs IBSC. They also provide an essential understanding of the properties of these solar cell structures in order to enhance further their efficiencies.