A Family of DC–DC Converters Deduced From Impedance Source DC–DC Converters for High Step-Up Conversion

A family of dc-dc converters based on impedance source dc-dc converters is presented. The scheme of the proposed family is that the switch of impedance source dc-dc converters is moved forward. The derived topologies are suitable for high-voltage step-up ratio. Compared to the typical impedance source dc-dc converters, the presented topology dramatically reduces the voltage stresses on the power semiconductor devices. In addition, the passive lossless clamped circuit is introduced into the proposed family to restrict the peak voltage of the main switch. This paper presents an analysis of the converter and results from a prototype converter to validate the topology's performance.


A. X-source DC-DC converters
It is known that the X-source network can be applied to DC-DC, DC-AC, AC-AC and AC-DC power conversion [13] . Among four conversion forms, the DC-AC power conversion is the most widely studied.
The DC-DC converters stem from X-source network have recently been studied. By adding the typical boost converter output structure, X source DC-DC converters can be obtained. As shown in Fig.2, Y source DC-DC converter can efficiently boost the low voltage to the high voltage [15] .

B. The existing problems in X-source DC-DC converters
Based on Fig.3, the generalized X source DC-DC converters structure can be represented as shown in Fig.4 (a). As the voltage stress on the power switch is equal to the output voltage, it is impossible to use the low voltage rated MOSFET. This is not beneficial for the improvement of performance of the converter. Therefore , how to find a way to reduce the voltage stress on the power switch, this is the key point.
The generalized X source DC-DC converter structure (b) The essence of reducing the voltage stress on the power switch

C. The deduced high step-up DC-DC converters with reduced voltage stress on MOSFET
The essence of reducing the voltage stress on the power switch is adding the voltage source between the output capacitor and the power switch as shown in Fig.4 (b). Therefore, in order to make the low voltage rated MOSFET available, the power switch S in the X source DC-DC converters can be reasonably moved forward, meanwhile, the position of some components need to be changed. Then, a family of basic high step up DC-DC converters can be deduced as shown in Fig.5. According to the basic inductor voltage-second balance principle, Table I shows the gains and switch voltage stresses of converters from Fig.5.   shows the equivalent circuit of the proposed converter (where I = I~V). Among Fig.6 (b), the coupled inductor is modeled as the magnetizing inductance M L , the leakage inductance k L and ideal transformer.

 
The operational waveforms of the proposed converter

A.CCM Operation
In the CCM operation, there are five operating modes in one switching period of the proposed converter. Fig.7 shows the operational waveforms and Fig.8 shows the current-flow path of the proposed converter for each modes. Here, the operating modes are described in detail.
Mode I [ 01 , tt ]: In this transition interval, the switch S starts to conduct. The diodes 1 D and 2 D are reverse biased. Diode o D is forward biased. The current-flow path is shown in Fig.8 Fig.8

A. Voltage gain expression
When the proposed converter operates in CCM mode, since the time durations of modes I and III is very transient, therefore, the two modes are neglected. During the time duration of mode II, the following equations can be expressed based on Fig.8 During the time duration of mode IV, the following equation can be derived as, During the time duration of modes IV and V, the following expression can be written as, By applying the volt-second balance principle on magnetizing inductor M L , the following equation is given, And substituting (1) and (3) into (4), collecting the terms, the voltage expressions of capacitor From (1), (2) and (6), the voltage stress on the capacitor 1 C can be obtained as Finally, based on the equations (4), (7) and (8), the voltage conversion gain can be computed as The schematic of the voltage gain versus the duty cycle under various coupling coefficients is shown in Fig. 9. It is seen that as the K decreases, the voltage gain increases. When K is equal to 1, the ideal voltage gain is written as  Fig.9 The effect of the coupling coefficient on the voltage gain under N=2 Fig.10 shows the ideal voltage gain comparison versus the duty ratio and turns ratio of the proposed converter as compared with the converters in previous papers [4] and [7]. As the turns ratio N decreases, the voltage conversion gain increases dramatically. This performance is contrary to other high step up DC-DC converters.

B. Voltage stress analysis
According to the above analysis, the voltage stresses across the switch S and diodes are derived from The voltage stresses on the power switch S and diodes related to the output voltage and turns ratio can be expressed as The relationship between the normalized voltage stresses on the semiconductor components and the turns ratio N is illustrated in Fig. 11. As the turns ratio decreases (voltage gain increases), the voltage stresses of switch S and diode D1 also decrease. Although the voltage stresses of diodes D2 and Do are increased, it is below the output voltage.   (20) According to the magnetic flux conservation principle and Fig.12

D. The effect of parasitic parameters on the voltage gain
In fact, the winding resistances of the coupled inductor, the conduction resistors of switch, and diode forward voltage have a little impact of the voltage gain. To simplify voltage gain analysis affected by the parasitic parameters, the leakage inductance is taken as zero. The primary sides and secondary sides of coupled inductors are equaled to 1 N R and 2 N R , respectively. The conduction resistor of switch is equaled to S R . The diode forward voltage is equaled to d V and the resistors of diodes are equaled to d R . Fig.13 shows the simplified circuit affected by the parasitic parameters of proposed converter, where j t is Fig.13 Simplified circuit for voltage gain analysis affected by parasitic parameters From Fig.13 and Fig.12 When the switch is turned off, the voltage across the winding 1 N can be expressed as   Combining (25)-(28), and collecting terms, then the voltage gain can be obtained as Where, It can be seen that the voltage gain is affected by the parasitic parameters including resistors and diode forward voltage. Once the circuit components are ideal, expression (10) can be obtained. In fact, the parasitic resistors of the circuit component are rather smaller than the output resistor. Therefore, their impact on the voltage can be ignored in practical circuit design.

VI Leakage energy solution of other converters
The passive-lossless clamp scheme can be employed for other deduced converters in part II as shown in Fig.14. With the simple but effective passive lossless circuits, the leakage energy is recycled and the voltage spikes are absorbed. So the efficiency of the converter is improved [20] .

VII Experimental verification
A 400W prototype converter with high step up ratio has been implemented and tested. Table I shows the specifications and circuit components, respectively, used in the proposed converter. V is also about 130V. Fig. 15 (b) shows the measured waveforms of D2 V and Do V . The voltage stresses on them is about 260V. Fig. 15 (c) shows the experimental waveforms of all the capacitors. The voltage stresses, Cc V , C1 V and o V are respectively about 130V, 180V and 380V. Fig. 15 (d) and (  The experimental RMS of the power switch current is in contrast to the theoretical value based on equation (24), as shown in Table II. Because of parasitic parameters, measurement error and so on, they are not absolutely the same. But, equation (24) can still be a good reference for choosing the switch. The efficiency of the proposed converter measured per 50W is illustrated in Fig.16 Fig.16 Test efficiency of the proposed converter VIII Conclusion In this paper, a family of DC-DC converters is deduced from impedance source DC-DC converters for high step up conversion. The voltage ratio characteristic of impedance source converters is used in the proposed converters, and the shortcomings of the impedance source converters, i.e. high voltage stress on mosfet, are avoided. The voltage stresses on the switches in the proposed converters are greatly reduced.
In addition, in order to suppress the voltage spike induced by the leakage energy, the passive clamp circuit is applied. Therefore, it makes the low resistance mosfet available, and the efficiency is improved. At last, the experiment results verify the theoretical analysis.