Suppression of First Sideband Switching Harmonics Using DC–DC Converters With an Advanced Modulation Scheme

The common dc-bus concept has become an attractive solution for future aircraft electrical power systems. This article considers the case where a battery connected dc–dc converter and a permanent magnet generator connected ac–dc converter are supplying a common dc bus. Applying a proper modulation scheme for dc–dc converters, suppression of the first-band harmonics (<inline-formula> <tex-math notation="LaTeX">$f_{c} \pm 3f_{0}$ </tex-math></inline-formula>) from the ac–dc converter can be achieved. The proposed harmonic suppression scheme essentially uses the fact that two sinusoidal waveforms with phase shift of <inline-formula> <tex-math notation="LaTeX">$\pi $ </tex-math></inline-formula> will counteract to each other. For an aircraft engine driving generator, the fundamental frequency <inline-formula> <tex-math notation="LaTeX">$f_{0}$ </tex-math></inline-formula> is time-varying and dependent on aircraft engine speeds. This time-varying <inline-formula> <tex-math notation="LaTeX">$f_{0}$ </tex-math></inline-formula> is normally derived with a resolver and some measurement error is expected. To ensure the effectiveness of the proposed harmonic suppression scheme, an enhanced pulse width modulation (PWM) compensation scheme has been proposed and implemented every fundamental cycle when the rotor position is detected a zero crossing. The effectiveness of the proposed suppression scheme is validated by experimental results with selected <inline-formula> <tex-math notation="LaTeX">$f_{c} -3f_{0}$ </tex-math></inline-formula> component for one dc–dc converter.


I. INTRODUCTION
M ORE electric aircraft (MEA) concept has been one of the major trends toward future aerospace development due to its decreased fuel consumption and low maintenance cost [1], [2]. To provide more sufficient and reliable power supply, single dc-bus power generation system with parallel-connected generators and battery systems has attracted significant interest [3]. Fig. 1 shows a conceptual diagram of this structure. Expected benefits that can be achieved include less need of cables, convenient integration of energy storage system, and higher redundancy ability under fault condition.
In the dc power generation system shown in Fig. 1, the capacitor bank is used to filter out high-frequency fluctuated currents and flatten the dc-bus voltage [4], such that the dc-bus voltage meets the DO-160E [5] and MIL-STD-704F [6] standards. This article is to further optimize the system shown in Fig. 1 and minimize the harmonics on the dc-bus capacitors. Capacitors are always bulky and expensive. Minimizing harmonics on the capacitor is critical which can potentially reduce size and improve maintainability of the capacitor [4].
Active suppression method is to adjust the switching actions of power converters to minimize the harmonics across capacitors. It has received significant attention recently because of its high flexibility and effectiveness. In [7]- [9], solutions with additional circuits are investigated for reducing switching frequency harmonics on capacitors. Those methods require extra power electronic elements and thus increase the cost and complexity of systems.
Without using additional device, some methods minimize the dc-link harmonic based on active control of the existing converters. In [10], the capacitor current ripple is reduced by applying nonadjacent switching vectors. In [11] and [12], harmonics on a dc capacitor were reduced on paralleled threephase voltage-source converters through a fixed phase-shift angle on converters. In [13], capacitor harmonics of a dual-generation system are suppressed by applying a 90 • phase shift on the carrier signal between two ac-dc converters. However, only ac-dc converters supply the dc-link in [10]- [13], which is not the case shown in Fig. 1.
For the system with dc-dc converter, as shown in Fig. 1, modifying the control of dc-dc converter has been well studied to suppress the dc-link harmonics. In [14], suppressed capacitor harmonics are achieved by reducing dc-link voltage using the dc-dc converter. However, the dc-link voltage becomes variable, which is not the case in the dc power system (the dc voltage should be constant in dc power systems). Lu and Peng [15] developed a modified pulse width modulation (PWM) scheme to minimize dc-link harmonics when a boost converter is connected to a two-level dc-ac converter. In [16], dc-link harmonics are suppressed by a real-time calculation of phase-shift angle on the dc-dc converter.
In these publications, most of the methods only focus on suppressing harmonics in the second switching frequency. For example, in [15] and [16], the switching frequency of the dc-dc converter is fixed as twice of that on the ac-dc converter. However, first-band harmonics are also nonnegligible on dc-link harmonics. In MEA, the permanent magnet synchronous generator (PMSG) is always driven by a high-speed shaft of the engine, thus it should work under flux-weakening control with a high modulation index. When the modulation index is higher than 0.9, the first sideband harmonic will cause higher voltage fluctuation on the dc-link capacitor [11], [17]. In the dc power generation system of MEA, to the best of the authors' knowledge, there are so far very limited publications addressing suppressing components in the first sideband switching harmonics. The reasons for the limited research are as follows.
1) There is more than one component in the first switching band, and their frequencies are adjacent. Therefore, it is difficult to filter out an exact component and measure the frequency and phase angle of it. 2) To suppress harmonic in the first switching band, the fundamental frequency of ac-dc converter is time-varying and potentially measured with minor errors. This will result in accumulated errors when applying harmonic suppression scheme.
In this article, we will fill these gaps and focus on suppressing harmonic on the first sideband harmonic. A harmonic estimation model of the first-band harmonic from ac-dc converter is provided to solve the first difficulty. For the second difficulty, the measuring error will cause an accumulated error, and compensation should be applied. Xu and Gao [18] proposed a method to compensate the accumulated error when the two digital controllers are with a tiny error of crystal frequencies. The switching frequencies of the converters are the same, and the compensation can be applied at any time. However, this is not the case in our method, as the dc-dc converter is involved, and the two carrier frequencies are different. Therefore, this article proposes an enhanced PWM compensation method. In the proposed method, accumulated errors are compensated in each fundamental cycle, and as a result, the dc-link harmonics show a suppression effectively in consistency.
The article is organized as follows. Section II gives the basic principle of the proposed harmonic suppression method. Section III presents the impact of the measured fundamental frequency errors which will impose challenges on the effectiveness of harmonic suppression. Section IV gives the proposed PWM compensation method. Section V validates the proposed suppression method and the PWM compensation method with experimental results. Lastly, the conclusion is given in Section VI.

II. PROPOSED CAPACITOR HARMONIC MINIMIZATION METHOD
A more detailed system of the dc power generation center is shown in Fig. 2. The voltage of the dc-link is 270 V which is the developing trend of the future electric power system [6]. Comparing to 28-V dc power system, higher dc-link voltage results in lower output current at the same rated power. Therefore, a lower cable diameter can be achieved which will benefit the system. A PMSG supplies electrical power to a dc bus through a two-level ac-dc converter. A high-voltage battery supplies power to the dc bus via a dc-dc converter. The battery is mainly to provide a flexible power flow, and thus the system performance (i.e., efficiency, fault tolerance) can potentially be improved. For the battery capacity, it is determined by the desired optimized objectives. Meanwhile, a bidirectional buck-boost converter is chosen because of its simple structure and high reliability. The ac-dc and dc-dc converters share a common dc-link capacitor. The two converters are controlled with their local primary controllers. A system controller is also used for high-level supervision (secondary) control. The system-level control is to define the power sharing between PMSG system and the battery. This is achieved by defining their load current references (I . The local controllers of ac-dc and dc-dc converters will receive command and control ac-dc converter and dc-dc converter to inject required dc currents to the dc bus. Fig. 3 shows the harmonic spectrum of the dc-link current (i dc ) from the PMSG system when the ac-dc converter works under sinusoidal PWM (SPWM). It can be noticed that significant components of the current harmonics are observed in f c ± 3 f 0 and 2 f c . In [11], we used harmonic components (which is of the frequency 2 f c , f c is the carrier signal frequency) generated from one ac-dc converter to suppress that from another ac-dc converter. Within this section, we will build upon our previous findings and explore the potentiality to use a dc-dc converter to suppress harmonics from an ac-dc converter, especially the f c ±3 f 0 components (where f 0 is the fundamental frequency). The proposed method is illustrated by focusing on the f c − 3 f 0 harmonic component studies.

A. Harmonic Analysis of a Two-Level AC-DC Converter
This harmonic analysis of a PMSG connected ac-dc converter has been well studied in [11]. There, we pointed out that the current harmonic component of f c − 3 f 0 frequency from the PMSG connected ac-dc converter can be expressed as where i d and i q are d-and q-axis currents, J n () is the Bessel function of the first kind, M is the modulation index, θ c is the phase angle of the carrier signal, α is the phase angle between fundamental ac currents and voltages (i.e., power factor angle), and β is the phase angle of ac current with reference to the electrical generator back-EMF. In (1), it is assumed that when t = 0 s, the machine rotor position is aligned with phase A (no initial angle). Angles α and β can be achieved from voltages and currents in dq-frame which are where v d and v q are d-and q-axis voltages, respectively. The function Arg() gives the angle of complex number (x + j y). From (1), the phase angle (θ With measured currents i d , i q , voltage references v d , v q , and modulation index M, the information of harmonic component f c − 3 f 0 , i.e., i dc,1,−3 (t), can be derived using (1)-(3). Its phase angle θ [g] dc,1,−3 can be derived from (4). Information of the ac-dc converters, i.e., i d , i q , v d , v q , M, and f c − 3 f 0 , will be sent to the controller of the dc-dc converter, as shown in Fig. 4. For the PMSG control, a cascaded control structure has been used, with current control being the inner loop. A flux-weakening control is applied in the outer control loop. This is due to the fact that in MEA applications, PMSG is driven by the high-speed shaft of an aircraft engine. The stator output voltage (v 2 d + v 2 q ) 1/2 is controlled by injecting a negative flux current component i d . The output current i dc of the ac-dc converter is also controlled with its reference i [g] * dc given by the system-level controller.
In Fig. 4, it can also be seen that a compensation pulse is generated when the rotor position hits zero. The usage of these information will be discussed in Section IV-B.

B. Harmonic Analysis of Bidirectional Buck-Boost DC-DC Converter
Switching signals from a buck-boost dc-dc converter (shown in Fig. 2) are normally generated by comparing the duty cycle reference and the carrier signal with a triangle waveform as shown in Fig. 5.
The two switches S 1 and S 2 are operated in a complementary manner. If the carrier signal is above the duty cycle line, switch S 1 is ON. If the carrier signal is below the duty cycle line, switch S 2 is ON. With this switching pattern, the current i [b] dc is generated and its spectrum is shown in Fig. 6. It can be seen that harmonic components are essentially around switching frequencies and its multiple times (i.e., f [b] c , 2 f [b] c , . . .). The first switching harmonics of f [b] c is of most significance and this component will be used to suppress the f c −3 f 0 from ac-dc converter.
To simplify the analysis, it is assumed that the inductor current is constant as I L and the converter works under continuous current mode. Thus, the dc current flowing into  the dc-bus capacitor, i [b] dc , can be given as Considering its symmetry, the current i [b] dc in (5) can be expressed using Fourier expansion as where From (6), it can be seen that the phase angles of i [b] dc harmonics depend on the carrier signal phase angle θ [b] c . In addition, the Fourier coefficients in (6) are given as sin(kπ D).
As mentioned before, this article illustrates to use the dc-dc converter to suppress the first sideband harmonic from an ac-dc converter (i.e., f c −3 f 0 ), thus only the first harmonic from the dc-dc converter, i.e., k = 1 in (6) and (9), will be used. This harmonic is denoted as i [b] dc,1 and can be expressed as From (10), it can be concluded that active control of the phase angle of current i [b] dc can be achieved by adjusting the carrier signal's phase angle θ [b] c . In practice, the battery current i L is not constant, but with a ripple I L (peak-to-peak), and I L is always designed to be within 0.2I L . In digital controller, measuring I L will make the control complicated. Hence, we neglect I L and use (10) to predict i [b] dc,1 . To evaluate the influence of neglecting I L , we calculated the errors of magnitude and phase angle when considering the ripple, as shown in Fig. 7(a) and (b). Under any duty cycle (D), the magnitude error is within 0.15%, which is quite neglectable. Meanwhile, the error of phase angle is less than 3 • . Compared to desired phase angle difference (180 • ) which will be discussed in Section II-C, 3 • error will not cause significant reduction of harmonic suppression effect.

C. Proposed Harmonic Minimization Method Using DC-DC Converter
Our proposed current harmonic suppression scheme essentially is based on the fact that two sinusoidal currents of the same magnitude will counteract each other if they are of 180 • phase shift. With this fact, we can use i [b] dc,1 from the dc-dc converter as an active harmonic injection source to cancel the f c − 3 f 0 harmonic component from the ac-dc converter i dc,1,−3 (t). To achieve that, the frequency of the carrier signal ( f [b] c ) of the dc-dc converter should be set to f c −3 f 0 , that is, To achieve the phase angle difference of 180 • between two harmonics, the phase angle of the PWM carrier signal in the battery connected dc-dc converter should be set as where θ [b] c is the phase angle of the carrier signal of the dc-dc converter and θ [g] dc,1,−3 is the phase angle of the carrier signal of the ac-dc converter.
With (11) and (12), the modulation scheme of the dc-dc converter control can be developed as shown in Fig. 8. There, the carrier frequency c ) is set to be f c − 3 f 0 and its phase angle θ [b] c is set to be θ dc,1,−3 + π using information from PMSG control system and (2)-(4). Together with the duty cycle D, the modified PWM signals are generated.
For the bidirectional buck-boost converter, the inductor is designed to limit the current ripple of i L ( I L ). With a lower switching frequency, the converter will generate higher I L . Hence, the inductance should be designed when the switching frequency is set as where f max 0 is the maximum value of f 0 .

III. IMPACT OF SWITCHING FREQUENCY ERRORS
In Section II, we have pointed out that setting the carrier dc,1,−3 + π, the first sideband harmonic of f c − 3 f 0 from the ac-dc converter can be suppressed using the first harmonic component from the dc-dc converter. However, during implementation, setting One reason is that although the modulation frequency f c for the ac-dc converter is set by the controller, the frequency f 0 is a measured valuef 0 and is normally derived from a PMSG speed resolver. Since the measured frequencyf 0 is subject to some degree of errors because of the resolution of the position sensor, it can be concluded that using this measured f 0 can potentially result in discrepancies between f [b] c and f c − 3 f 0 . This, in return, will undermine the performance of harmonic suppression since this error (which can be tiny) will be accumulated and resulted in significant difference between θ [b] c and θ [g] dc,1,−3 +π. As a result, the effectiveness of harmonic suppression cannot be achieved at all.
Meanwhile, if each converter is using their local controller, the frequencies of crystals inside digital controllers cannot be exactly the same, which will induce the deviation between f c andf c [11].f c is the "virtual" switching frequency if the digital controller of ac-dc converter uses the same crystal of dc-dc converter. In this case, communication between the two local controllers should be designed, i.e., CAN, RS485. Fig. 9 illustrates a scenario of the case when f [b] c and f c − 3 f 0 are not equal due to the errors. There, two components, i.e., i 1 (t) and i 2 (t) are used to represent harmonic components of f [b] c (assumed to be f 1 ) and f c − 3 f 0 (assumed to be f 2 ) from dc-dc and ac-dc converters, respectively. Due to the error in f c and f 0 , the carrier frequency 96 : 1 and these two harmonic components have a phase difference of π initially. These two components counteract each other fully at the beginning. However, due to the discrepancy of the two frequencies, the phase difference between these two is actually fluctuating instead of being a constant value of π. Thus, the two components are essentially modulating each other rather than suppressing each other as shown in Fig. 9.
To mitigate the impact of such f 0 measurement error and achieve an effective suppression in a consistent way, compensation of such error is essential. This will be discussed in Section IV.

A. Applying Compensation to Avoid the Accumulated Error
As discussed before, error of f [b] c will lead to a situation that the phase angle of the targeted harmonics from the ac-dc converter and the dc-dc converter are fluctuating rather than of π phase shift. To mitigate the impact of this error, compensation should be applied before this error becomes significant. One way to mitigate such accumulated error is simply resetting the phase angles as shown in Fig. 10. It can be seen that adding two components (i 1 and i 2 ) with initial π phase difference and very small frequency discrepancies will result in a fluctuated waveform. However, to avoid situation in Fig. 9, compensation will be applied when the accumulated error is not significant (π/6 in Fig. 10). The compensation essentially is to reset the phase angle of i 2 (t) to be with a π phase difference again compared to that of i 1 (t). After each compensation, although the error between i 1 (t) and i 2 (t) will be accumulated again, the error can be always kept within a tolerable range by taking compensation actions in every a few cycles.

B. Compensation Instant Identification
The same concept in Fig. 10 can be used to mitigate the errors off c andf 0 when setting the frequency of PWM carrier signal within the dc-dc converter f [b] c to be f c −3 f 0 (in reality it isf c − 3f 0 ). One of the key implementation aspects of the compensation is to identify the time instant when to apply such compensation.
Considering the fact that f 0 varies according to the rotor speed of PMSG, the carrier frequency of the dc-dc converter ( f c −3 f 0 ) is thus not fixed. On the other hand, the carrier signal of the ac-dc converter is a triangle waveform with a fixed frequency and phase angle. In that case, we can take the carrier signal of the ac-dc converter (of frequency f c ) as the reference signal. The carrier signal (of frequencyf c − 3f 0 ) of the dc-dc converter needs to be compensated every a few cycles to avoid accumulated error as it should be with a frequency of f c −3 f 0 . One potential good choice is to select the compensation time instant to be when the PMSG rotor position is detected "Zero." It is a very logic selection as a fundamental cycle of the PMSG is a reasonable small amount of time and the zero-detection signal from rotor position is convenient to derive in practice.
As shown in Fig. 11, a compensation pulse is generated when rotor position θ r hits zero. The controller of the ac-dc converter sends this pulse together with information for phaseshift angle calculation, i.e., i dq , v dq , M, θ c , to the controller of the dc-dc converter, as shown in Fig. 12.
After the dc-dc controller receives the pulse, compensation will be applied immediately. At that time instant, the frequency of the dc-dc converter carrier signal will be refreshed to a newf c − 3f 0 at that time instant. A time shift ( T ) of the carrier signal will also be applied to the dc-dc converter   microcontroller as shown in Fig. 13. This time shift T is given as  In the digital controller, we used during experiment (TI DSP TMS320F28379D), the carrier signal is generated from a time-base counter [20]. The desired time shift T is achieved by setting the proper counting direction and the initial counting value when the compensation pulse comes.

V. EXPERIMENT RESULTS
To validate the proposed harmonic suppression scheme, an experimental rig has been set up as shown in Fig. 14. PMSG is represented by a programmable ac source together with three-phase inductors. A phase-locked loop (PLL) is implemented in the controller to achieve the phase angle of fundamental ac voltages. The battery system is represented by a dc power supply which is connected to a dc-dc converter. Since the harmonic suppression scheme is related to ac-dc and dc-dc converter, using a three-phase ac source and a dc power supply to represent the PMSG and battery will not really affect the effectiveness of the proposed harmonic suppression scheme. The dc source is used to represent the battery with a constant voltage output of 200 V. The system is controlled using TI DSP TMS320F28379D. The parameters of the experiment are shown in Table I. The total output power of the ac-dc converter and the dc-dc converter is 2 kW. The ac fundamental frequency is 50 Hz. The switching frequency of the ac-dc converter, f c , is set at 4000 Hz. However, to emulate the two converters controlled by two digital controllers (thus with different crystal frequencies), f c is set as 4.00016 kHz. When no harmonic suppression scheme is applied, the dc-dc converter uses the "same" carrier signal as that of the ac-dc converter with is 4 kHz, which means f [b] c1 = 4 kHz. For the proposed suppression method, the carrier signal frequency of the dc-dc converter ( f [b] c ) is set to be f c − 3 f 0 , i.e., 3.85 kHz.
The experimental diagram is the same as Fig. 12. The ac-dc and dc-dc converters supply the dc-link according to the reference sent by the system-level controller. DC-bus currents, including i dc , and i cap , are measured to validate the proposed method. The effectiveness of suppression can be validated more obviously in frequency domain, and thus fast Fourier transform (FFT) results of i cap will be given in the following analysis.
When the dc power system works without harmonic suppression scheme, Fig. 15 shows the dc-bus currents from the ac-dc converter and the dc-dc converter (i [g] dc and i [b] dc ). The current flowing into the capacitor i cap and its spectrum are shown in this figure. Both converters use the same carrier signal. The ac-dc converter generates harmonics on f c ± 3 f 0 and 2 f c , and the dc-dc converter generates harmonics on f c and 2 f c . These components are summed up together on the dc-link capacitor current.
To suppress the f c − 3 f 0 harmonic, the carrier frequency of the dc-dc converter is set as f c − 3 f 0 , i.e., 3.85 kHz. As discussed in Section III, the accumulated error caused by measuring error off c andf 0 will undermine the performance of harmonic suppression scheme and result in a fluctuating component. Two screenshots from scopes are shown in Fig. 16 We also record a video to clearly show the fluctuation of this component.
To compensate this accumulated error, the proposed suppression method together with the PWM compensation scheme  are implemented. Compensation pulses are generated in every 20 ms (50 Hz), which is the same as the periods of fundamental ac voltages, as shown in Fig. 17. It can be seen that, with continuous compensation in every fundamental cycle, the f c − 3 f 0 harmonic can be suppressed in consistency, as shown in Fig. 17. Compared with the case without harmonic suppression scheme in Fig. 15, harmonic in the frequency of f c − 3 f 0 is suppressed from 2.24 to 0.42 A (81.2% reduction). For harmonic of the frequency f c , there was a component with 2.08 A in the conventional case (Fig. 15), but no component showing in f c when the proposed method is applied (Fig. 17). This is because the switching frequency of the dc-dc converter is changed from f c to f c − 3 f 0 . It is also interesting to notice the change of second-order harmonics of i cap . With the proposed scheme, there are two components on the second band, i.e., 2 f c and 2 f c − 6 f 0 . The 2 f c is from the ac-dc converter, the 2 f c − 6 f 0 component is actually from the dc-dc converter. This does not mean that the proposed scheme will generate more harmonics at the second switching frequency level. Actually, without using the harmonic compensation scheme, both ac-dc and dc-dc converters will generate 2 f c components and these two components will add on each other at 2 f c in the spectrum. The suppression scheme helps reduce the root mean square (rms) value of i cap from 3.98 to 2.93 A (26.4% reduction). This will extend the lifetime of the capacitor because a lower hotspot temperature can be achieved with lower rms current. To further validate the effectiveness of the proposed PWM compensation method, a video is given to show the comparison between the spectrums with and without PWM compensation as the time elapses.
The experimental results are conducted, when the load changes from 2 to 3 kW, as shown in Fig. 18(a). Because of the large scale (200 ms/div) on the oscilloscope, the capacitor current (i cap ) shows a large distortion, and thus it will not be shown in Fig. 18(a). The output power of dc-dc converter remains the same, and the ac-dc converter compensates the 1-kW step change. The dc-link voltage (V dc ) shows a drop and recovery after the load change. Meanwhile, a higher output power of the ac-dc converter results in a variation of the phase angle of f c −3 f 0 component (θ [g] dc,1,−3 ), as shown in Fig. 18(a). When the system operates back to steady state, the total output power is 3 kW. The proposed method can still effectively suppress the f c −3 f 0 on i cap , as shown in Fig. 18(c). Compared to the case without suppression [ Fig. 18(b)], f c −3 f 0 harmonic of i cap is suppressed from 2.29 to 0.45 A (80.3% reduction). The rms value of i cap is also reduced from 5.13 to 4.49 A.

VI. CONCLUSION
For a dc power generation system in MEA, this article proposed a suppression method of dc-link harmonic in the first switching band frequency. The method is to actively adjust the switching frequency and phase-shift angle of the carrier signal in the battery system. An enhanced PWM compensation method is also proposed because there are measuring errors on the ac fundamental frequency. Finally, the experiment results are given to validate the effectiveness of the proposed suppression method. The new PWM compensation scheme is proven to provide a continuous suppression on the dc-link harmonic. The proposed work is extremely useful to improve the power quality of the power electronic dominated dc grid in consistency. The lifetime of the dc-link capacitor can also be extended.