The Alternate Arm Converter “Extended-Overlap” Mode: AC Faults

This article presents ac fault ride-through strategies for the “extended-overlap” operating mode of the alternate arm converter (AAC), which is a type of modular multilevel voltage source converter that has been proposed for HVdc transmission applications. The AAC offers several benefits over the half-bridge modular multilevel converter, such as requiring fewer submodules with a smaller capacitance and providing dc fault ride-through capability. Novel symmetrical and asymmetrical ac fault ride-through strategies are described and these strategies are experimentally validated by using a small scale prototype.


I. INTRODUCTION
T HE modular multilevel converter (MMC) [1] is presently the preferred voltage source converter (VSC) topology for commercial HVdc installations [2] due to the half-bridge (HB) submodule (SM) variant having an efficiency of ≈99% [3]. Additionally, this converter generates high-fidelity ac side voltages, thereby easing filtering requirements [1], [4], [5]. In each converter arm, hundreds of SMs are series-connected to form a valve and the charged capacitors in each SM are switched into the circuit with positive polarity or are switched out of the circuit to generate a multilevel voltage. Each arm also comprises an inductor, which has the main purpose of limiting the fault current gradient and the corresponding current peak during dc side faults [6], before the relatively slow-acting ac side mechanical breaker is opened to disconnect the converter from the ac network, thereby breaking the fault current [7], [8]. Normally, these inductors do not cause voltage spikes during operation because the arm currents flow continuously [5].
The full-bridge (FB) SM variant of the MMC [9] can stay connected to the ac network and operate as a STATCOM during dc side faults because the valves can now generate positive and negative voltages, thereby allowing the ac side voltage to be opposed throughout a fundamental period so that uncontrolled diode conduction can be prevented. However, twice as many semiconductor devices are required [9] and the converter conduction losses double during normal operation [10]. In order to provide dc fault ride-through capability with fewer semiconductor devices, alternative SM arrangements, such as the "double-clamp" SM, have been proposed [11]. Alternatively, the "hybrid" MMC typically uses an equal number of FB and HB SMs so that dc fault ride-through is provided with 25% fewer semiconductor devices than the FB-MMC [12].
The alternate arm converter (AAC) is another type of modular multilevel VSC that has been proposed for HVdc transmission applications [13], [14]. The AAC offers several benefits over the HB-MMC, such as comprising typically 30%-40% fewer SMs [15], requiring approximately half the SM capacitance to yield a given SM capacitor voltage ripple [16], [17], and providing dc fault ride-through capability [18], [19]. In addition to each arm comprising a valve (formed by FB SMs) and an inductor, there is also a series-connection of self-commutated semiconductor devices with antiparallel diodes, termed a director switch (DS). A strategy is required to balance the voltages across the series-connected devices within a DS [20]. The two DSs in each converter phase-leg alternate conduction of the ac side current so that this current is rectified on the dc side. There is a handover period, termed "overlap," twice per fundamental period, where a controlled circulating current flows to enable SM energy management [21], [22]. When an arm is conducting the ac side current because its DS is closed, the corresponding valve is generating the multilevel ac side voltage for this phase. The valve in the other arm of the corresponding phase-leg generates a voltage which aims to ensure that the voltage across its DS remains positive so that the antiparallel diodes remain reversed biased.
A comparison of the HB-MMC, FB-MMC, and AAC attributes is shown in Table I [1], [9], [13]- [19]. The nominal SM capacitor voltage is equal for all converters. The number 0885-8993 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
of SMs, SM capacitance, and semiconductors is normalized to those required for a HB-MMC. The original AAC operation mode is termed "short-overlap," where the nominal "overlap" angular duration is in the region of 15 • -18 • [21], [23]. In this operation mode, the dc current contains a characteristic ripple at multiples of six times the fundamental frequency, which can be filtered by using a bulky passive low-pass filter [14], [21]. Alternatively, the electrical characteristics of the HVdc link along with dc link capacitance and additional damping resistance can provide the required filtering [23].
This article concerns the more recently disclosed "extendedoverlap" mode [24], [25], where the nominal "overlap" angular duration is 60 • [12]. This operating mode causes the ac currents sum to zero at a point within the converter and makes a conduction path for the dc current through a phase-leg always available and therefore a ripple-free dc current can be obtained [12]; this attribute is termed "active filtering" [24], [26]. As the dc current no longer has a characteristic ripple, a bulky passive filter is not required and therefore the related drawbacks of the AAC described in [27] are resolved. Additionally, as the dc side current is no longer coupled to the rectified ac side currents and as the "overlap" duration is longer, the AAC can operate more easily away from the "sweet-spot," where there is a natural ac and dc side power balance [14], [21], without requiring unrealizable circulating currents [12]. When operating with only a fundamental phase-neutral converter voltage component, a longer "overlap" duration increases the required valve voltage rating. However, by operating in the "extended-overlap" mode with an additional zero phase sequence (ZPS) converter voltage component, which cancels at the grid-side due to the transformer arrangement, the zero-crossing regions of the converter voltages can be "flattened" such that the required valve voltage rating is comparable to that for "short-overlap" operation, at the expense of increasing the required DS voltage rating by ≈60% [15]. Nonetheless, a DS voltage rating increase does not increase the cost or volume of the converter as much as an equal increase in the valve voltage rating, mainly due to not requiring additional costly and bulky SM capacitors [13], [28].
By using the small scale prototype (SSP) described in [29], AAC DC fault ride-through strategies described and validated by simulation in [18], [19], termed STATCOM mode "A" (where the mean dc side current equals zero) and modes "B1" and "B2" (where the instantaneous dc side current equals zero), are experimentally validated for the "extended-overlap" mode in [29].
Converters in HVdc applications are required by regulations such as [30] to remain connected to the ac network during periods of depressed voltage at the point of common coupling caused by ac faults, which vary in typical duration between hundreds of milliseconds for severe faults to a few seconds for minor faults. Depending on operator requirements and fault severity, the converters may be required to exchange reactive power with the ac network to provide ac voltage support during faults and continue to transfer active power, albeit potentially at a reduced level due to converter limits. After the fault is removed, prefault active power should be restored. Voltage or current protection should not be triggered at any point throughout the entire sequence. A consideration for modular multilevel VSCs during faults is to aim to ensure that the capacitor voltage of each SM still remains within normal operation limits so that the converter continues to operate properly and safely. MMC control strategies for SM capacitor voltage/energy management [31]- [34] and ac fault ride-through [35]- [37] are not directly applicable to the AAC because this topology is time-varying over a fundamental period due to the varying DS combinations [23], [38], unlike the MMC topology, which is time-invariant when the valves are approximated as controllable voltage sources [39]. AAC "short-overlap" mode control strategies for SM capacitor voltage management [22], [40], [41] and ac fault ride-through [42] cannot be directly applied to the "extended-overlap" mode due to the previously described operational differences between these two modes. Therefore, in this article, novel ac fault ride-though strategies for the AAC "extended-overlap" mode are described and then experimentally validated by using the SSP.
The remainder of this article is organized as follows. In Section II, the AAC "extended-overlap" mode is described in more detail. A symmetrical ac fault ride-through strategy is presented in Section III. In Section IV, considerations for operation during asymmetrical ac faults are introduced and ride-through strategies for single-phase and line-line faults are presented in Sections V and VI, respectively. In Section VII, the described ride-through strategies are experimentally validated by using the SSP. Finally, the conclusion is drawn in Section VIII.

II. CONVERTER TOPOLOGY AND OPERATION
The AAC is illustrated in Fig. 1, where x ∈ {a, b, c} is the phase identifier; v LWx , i LWx , v VWx , and i VWx are, respectively, the line winding (LW) and valve winding (VW) voltages and currents; v VUx , v VLx , i VUx , and i VLx are, respectively, the upper and lower valve voltages and currents; and v DSUx and v DSLx are, respectively, the upper and lower DS voltages. Each arm comprises a FB SM valve, an inductor, and a DS, which is formed by series-connected insulated-gate bipolar transistors (IGBTs) and antiparallel diodes. The ac side is a three-phase three-wire  system and the converter is interfaced to the ac network by using a star-delta transformer with a LW to VW turns ratio of 1 : N V W . This transformer winding arrangement is typical for HVdc-VSC schemes [43] and provides cancelation of the ZPS VW voltage on the LW side, during all conditions, so that distortion is not introduced to the ac side currents. However, other winding arrangements, which provide this cancelation, are also feasible. The positive and negative pole-ground dc voltages are denoted by V DCp and V DCn , and the positive and negative pole dc currents by I DCp and I DCn . All figures and values in this article are approximate and not definite in nature.
The AAC "extended-overlap" mode is described in detail in [12]. The operating principle of this mode is illustrated in Figs. 2 and 3 by showing nominal ideal waveforms of the phase "a" DS gate signals and system voltages (see Section II-A) and the three-phase system currents, for an example case where the VW voltage and current are in-phase (φ = 0). The ideal waveforms shown in this article (Figs. [2][3] are generated by MATLAB from equations. Taking phase-leg "a" as an example, when only the upper arm DS is closed [intervals where g DSUa = 1 and g DSLa = 0 in Fig. 2(a)], the upper valve is solely responsible for generating a positive VW voltage, as seen in Fig. 2(b) and (c), and the upper arm conducts the VW current, as seen in Fig. 3(a) and (b). The lower valve generates the voltage shown in Fig. 2(c), which aims to ensure that the lower arm DS antiparallel diodes remain reverse biased by having a positive voltage across this DS, as seen in Fig. 2(d). Conversely, when only the lower arm DS is closed [intervals where g DSUa = 0 and g DSLa = 1 in Fig. 2(a)], the lower valve is responsible for generating a negative VW voltage, as seen in Fig. 2(b) and (c), and the lower arm conducts the inverse of the VW current, as seen in Fig. 3(a) and (b). The upper valve now generates the voltage shown in Fig. 2(c), which aims to ensure that the upper arm DS antiparallel diodes remain reverse biased by having a positive voltage across this DS, as seen in Fig. 2(d).
When the upper and lower arm DSs are both closed [intervals where g DSUa = 1 and g DSLa = 1 in Fig. 2(a)], this is termed "overlap," which is a key terminology for the AAC. "Overlap" periods occur for a nominal angular duration of 60 • and are centred around the zero-crossings of the VW voltage, as seen in Fig. 2(b). In Figs. 2 and 3, the start and end of "overlap" periods for phase "a" and for the three phases, respectively, are indicated by the vertical dashed lines. During "overlap," both valves are responsible for generating the VW voltage, as seen in Fig. 2(b) and (c). The upper arm conducts half the VW current and the lower arm conducts the inverse of half the VW current. Additionally, both arms conduct the current component relating to the dc side power and, although not shown in the valve currents of Fig. 3 for the sake of clarity, smaller current components relating to SM capacitor energy regulation are denoted by I circ x (see Section II-B). Furthermore, both arms conduct current components relating to "active filtering" so that an ideally ripple free dc current can be obtained [24], [26]. When a DS is required to open at the end of an "overlap" period, "zero-current" turn-OFFis achieved by actually opening the DS when its antiparallel diodes are conducting [44] (not shown in the valve currents of Fig. 3 for the sake of clarity).
Taking as an example the 60 • interval in Fig. 3 where phaseleg "a" is in "overlap," phase-leg "b" has only its upper DS closed and phase-leg "c" has only its lower DS closed (0.0083 ≤ t < 0.0117), the valve currents are defined by (1). Similar valve current expressions can be found for the remaining five 60 • intervals of a fundamental period [12] i  Throughout a fundamental period, the valve currents of the three phases plotted in Fig. 3(b)-(d) obtain the sinusoidal VW currents shown in Fig. 3(a) and defined by (2), where x ∈ {a, b, c} ≡ k ∈ {0, 1, 2}. As the same circulating current is applied to both arms of the phase-leg that is in "overlap," the circulating currents do not appear in the VW currents. A ripple free dc current, defined by (3), is obtained due to the VW current components in the arms summing to zero in both dc pole currents and the circulating currents equalling zero in steady-state (see Section II-B) The AAC requires several controllers to regulate the active and reactive power components and each SM capacitor energy to their desired set-points. The control philosophy used in this article is described in [45]- [48] and is applicable not only to the MMC but also to the AAC when modifications are made to the control strategies for SM capacitor energy regulation and ac fault ride-through as well as considering DS operation. This control philosophy is effective when the converter is connected to strong or weak ac systems during symmetrical or asymmetrical conditions, without requiring a phase-locked loop. Fig. 4 illustrates the overall control strategy for the AAC, which is summarized here and described further in the following sections. The measured LW voltages, referred to the transformer VW side, are transformed to positive and negative phase sequence (NPS) components in the αβ stationary reference frame. A unified power controller independently regulates the measured dc side power (or dc voltage) and the measured reactive power (or ac voltage) to their orders by using PI controllers. The power controller outputs a reference ac side active power, which is trimmed to consider losses (see Section II-B), a reference reactive power, and a reference dc current. The reference ac side active and reactive powers along with the referred LW voltages are used to derive the reference VW currents. These references along with the reference dc current and the reference circulating currents related to SM energy management (see Section II-B) are used to derive the reference valve currents. Additionally, in order to facilitate DS "zero-current" turn-OFF, the corresponding reference valve current is made negative at the end of "overlap" [44]. A linear quadratic regulator controller is used to regulate the measured valve currents to their references by generating reference voltages for the valves. The reference valve voltages also include a ZPS component and are offset when the corresponding DS is open to aim to ensure the DS antiparallel diodes remain reversed biased. The reference valve voltages are synthesized by the SMs by using a level-shifted multilevel modulation scheme [49] and an SM rotation algorithm [31] is applied to each valve as the modulation scheme generates unequal SM duties. The instants at which a DS is required to open or close are derived from the VW voltage angular displacement and the "overlap" angle, but the IGBTs in the DS are only actually opened when the corresponding measured valve current is negative [44].

A. Reference Valve Voltages
Ideal reference valve voltages can be found from the VW voltages required for a given operating condition. The fundamental VW voltages are ideally sinusoidal waveforms and can be defined by (4). A ZPS component is introduced to "flatten" the VW voltage zero-crossing regions so that the valve voltage rating is reduced [15]. The ZPS component is nominally a triangular waveform with a period of a third of a fundamental period and is defined by (5) for 0 ≤ t < Φ OVx 2ω , where Φ OVx is the "overlap" angle and ω is the fundamental angular frequency; similar expressions apply for the remainder of a fundamental period. The same ZPS component is always applied to each phase, and, therefore, this component cancels at the LW due to the transformer arrangement. Given (4) and (5), the VW voltages are defined by (6). The nominal fundamental to ZPS component magnitude ratio is defined by (7) so that the required valve voltage rating is comparable to that of the "short-overlap" mode [15]. By using (4)-(7) with Φ OVx = π 3 rad and ω = 2π50 rad/s, the phase "a" VW voltages are plotted in Fig. 5 Ideal reference upper and lower valve voltages can be found by neglecting the relatively small arm inductor voltages and by assuming that When the upper or lower arm DSs are closed (g DSUx = 1 or g DSLx = 1), the reference valve voltages can be derived from V DC and v ref VWx . However, when the upper or lower arm DSs are open (g DSUx = 0 or g DSLx = 0), an offset of V os V is also applied to the valve voltages with the aim to ensure that the arm DS antiparallel diodes remain reversed biased. Consequently, the reference upper and lower valve voltages can be defined by (8) and (9), respectively v ref The reference valve voltages are plotted in Fig. 5(b) for nominal operation, when normalized to the dc voltage. The offset valve voltage V os V is selected to equal 2V nom sm , where V nom sm is the nominal SM capacitor voltage and is equal to 0.2 p.u. as its base is the dc voltage. The valve voltages are limited to 1 p.u. as this is the SSP valve voltage rating, but at the end of "overlap," the arms stop conducting the corresponding VW current, and, therefore, the corresponding valve stops generating the VW voltage (see Section IV-B). The valve voltages during "overlap" are of interest for SM capacitor energy management and are plotted in Fig. 6(a).

B. SM Capacitor Energy Management
The SM capacitor energies vary as they are charged or discharged by the valve currents. For sustained converter operation, the mean SM capacitor energies need to be regulated to the nominal value defined as follows, where C sm is the SM capacitance: The SM capacitor energy controller (SM energy management block in Fig. 4) is based on [45] and [46] but has been adapted for the AAC "extended-overlap" mode. The ac side power is trimmed by using a PI controller to account for losses so that the mean of the total SM capacitor energy stored within the converter is regulated to 6N sm E nom sm , where N sm is the number of SMs per valve. As the converter is operated around the "sweet-spot" [12], the ac side power trim is minimized.
In each phase-leg, the mean of the summed upper and lower valve SM capacitor energies is regulated to 2N sm E nom sm by using a PI controller, where the output of the PI controller is denoted by I ref DCcirc x . During steady-state symmetrical operation, these outputs are ideally zero due to the symmetry between converter phase-legs. The PI controller outputs for the three phase-legs are combined to form the controller actuators, termed the reference dc circulating currents I ref DCcirc x . The reference dc circulating currents are derived by using (11) so that over half a fundamental period (the duration of three "overlap" periods) they sum to zero in both dc pole currents. In each phase-leg, the reference dc circulating current component interacts with the voltage time area (VTA) of the summed valve voltages during "overlap" to cause a controlled net change in the summed upper and lower valve SM capacitor energy ⎡ In each phase-leg, the mean of the difference between the summed upper and summed lower valve SM capacitor energies is regulated to zero by using a PI controller, where the actuator is the reference ac circulating current I ref ACcirc x , and this component interacts with the VTA of the difference between the valve voltages during "overlap" to cause a controlled net change in the difference between the summed upper and summed lower valve SM capacitor energy. Ideally, in steady-state, the reference ac circulating current for each of the three phase-legs is zero due to the converter upper and lower arm symmetry. During transients, the ac circulating current appears instantaneously in the dc pole currents but, for a phase-leg, sums to zero over an "overlap" period because the ac circulating current for the first half of "overlap" is set to the inverse of that for the second half of "overlap." The reference dc and ac circulating current components form the reference circulating current I ref circ x , which is defined by (12) and is plotted in Fig. 6 Fig. 4

and described in this section
During "overlap," the four instantaneous energies shown in (13) can be defined. For the voltages and currents shown in Fig. 6, these energies are plotted in Fig. 7, when Φ OVx = π 3 rad. The plots show that the dc component affects the net change in energy of the summed upper and lower valve SM capacitors (ΔE DCsum x > 0) and that the ac component affects the net change in energy of the difference between the summed upper and summed lower valve SM capacitors (ΔE ACdiff x > 0). Whereas, the ac component does not affect the net change in energy of the summed upper and lower valve SM capacitors (ΔE ACsum x = 0) and the dc component does not affect the net change in energy of the difference between the summed upper and summed lower valve SM capacitors (ΔE DCdiff x = 0). Additionally, for this example case, ΔE DCsum x can be made negative by using a negative dc circulating current and ΔE ACdiff x can be made negative by inverting the ac circulating current

III. SYMMETRICAL AC FAULT RIDE-THROUGH STRATEGY
As the severity of a symmetrical ac fault increases, the fundamental VW voltage magnitude decreases toward zero. When using a constant fundamental to ZPS component voltage magnitude ratio, such as that defined by (7), the VTA during "overlap" of the difference between the reference upper and lower valve voltages decreases linearly toward zero. As this VTA decreases, the required ac circulating current magnitude has to increase to have the same effect as previously. Furthermore, if the circulating current limit is reached, the means of the summed SM capacitor voltages in the upper arm and those in the lower arm of a phase-leg begin to diverge from each other during the fault. Therefore, a ride-through strategy for symmetrical ac faults is proposed to aim to ensure that this VTA remains constant, even when the fundamental VW voltage magnitude varies from its nominal value. This is achieved by modifying the calculated ZPS VW voltage, which is input to the valve voltage generation block in Fig. 4. The amount of energy exchanged between the capacitors in the upper arm and those in the lower arm is controlled by varying ac circulating current magnitude, which is calculated by the SM energy management block in Fig. 4 (see Section II-B).
Integrating the difference between the reference upper and lower valve voltages, over the first half of "overlap" (0 ≤ t < Φ OVx 2ω in Fig. 6), yields the VTA defined by (14), where the phase identifier has been omitted due to symmetrical operation. As the converter has upper and lower arm symmetry, (15) can be written, where VTA2 is found when integrating over the second half of "overlap" ( Φ OVx 2ω ≤ t < Φ OVx ω in Fig. 6). If m ratio is kept constant asV fund VW reduces to zero, VTA decreases linearly to zero, as shown in Fig. 8 The dashed line in Fig. 8(a) indicates the nominal case, where VTA is defined by (16). By equating VTA with VTA nom and then solving for m ratio yields (17). As m ratio is a function of     (17), whenV fund VW varies from its nominal value, VTA can be maintained constant by compensating with m ratio . During symmetrical ac faults, m ratio is flexible because all valves have sufficient available voltage during "overlap" due to a reduction inV fund VW on all phases. Equation (17) is plotted in Fig. 8(b), where m ratio = −∞ whenV fund VW = 0 Residual VW voltages of 0.8, 0.5, and 0.01 p.u. are used to illustrate representative minor, major, and severe ac faults, respectively. These fault cases are given in Table II along   Regardless of the chosen transformer winding arrangement, the three-phase VW voltages are always displaced by 120 • during symmetrical ac faults (unlike asymmetrical ac faults described in Section IV). Therefore, this symmetrical ac fault ride-through strategy directly applies to other applicable winding arrangements.
Power losses when using the symmetrical ac fault ridethrough strategy, and when using the ride-through strategies for single-phase and line-line ac faults described in Sections V and VI, respectively, are not considered in this article. This is reasonable because losses for HVdc schemes are calculated for normal operation during steady-state [50], [51] and not during ac faults, which only occur for between hundreds of milliseconds and a few seconds, depending on the fault severity; otherwise, the converter is allowed to be disconnected from the ac network [30].

A. Further Assessment Criteria
The range of symmetrical ac faults with residual voltages down to 0 p.u. causes the largest change in the three-phase VW voltage vector magnitude, when compared to asymmetrical ac faults, and contains the worst-case fault (a three-phase to ground fault). Therefore, the symmetrical ac fault ride-through strategy is further assessed in terms of peak and rms valve currents, and peak-peak valve energy deviation.
An exemplar active and reactive power operating envelope for VW voltages down to 0 p.u. is derived. Given the VW voltage and current conventions of Fig. 1, positive active power indicates that the converter is inverting and positive reactive power indicates that current is lagging voltage to provide ac voltage support. The envelope is based on the following constraints: The maximum VW current magnitude occurs at rated active and reactive power (P = 1 p.u. and Q = 0.4 p.u.) with a VW voltage magnitude of 0.9 p.u.; reactive power is prioritized over active power when the VW voltage magnitude is <0.9 p.u.; and active power is zero when the residual VW voltage magnitude is ≤ 0.5 p.u. [30], [52]. In Table III, the VW current magnitude, phase angle between VW current and voltage, active power, and reactive power are shown for the VW voltage magnitude range.
Due the converter upper and lower arm symmetry, only the upper arm is considered in the following analysis. By using (4)-(6), (8), and (17), the upper valve voltages, across the VW   Fig. 12(a). By using (1a) (and similar expressions for the remaining five 60 • intervals of a fundamental period), (2), and Table III, the upper valve currents are plotted in Fig. 12(b). The peak and rms valve currents are shown in Table IV. The largest peak and rms valve currents occur with a VW voltage magnitude of 0.9 p.u. because rated active and reactive power is maintained. The upper valve power is found by multiplying together its voltage and current and is plotted in Fig. 13(a). This power can  be integrated to find the upper valve energy deviation, which is plotted in Fig. 13(b). The peak-peak valve energy deviations are shown in Table IV. The largest peak-peak valve energy deviation occurs during the worst-case fault, where this value is 2.3 times that for nominal operation. However, the peak-peak valve energy deviation for an MMC with a residual ac side voltage magnitude of just 0.9 p.u. is already three times that for an AAC [17].

IV. ASYMMETRICAL AC FAULTS
Determining the propagation of asymmetrical ac faults at the LW through the wye-delta transformer and determining the maximum valve voltage when an arm is conducting the VW current during nominal operation are both required for developing the asymmetrical ac fault ride-through strategies described in Sections V and VI.

A. Propagation of Asymmetrical AC Faults Through the Wye-Delta Transformer
In the Appendix, the phase-neutral referred LW (RLW) voltages, which are the LW voltages referred to the transformer VW side, are defined in terms of the phase-neutral LW voltages in (23) so that the propagation through the wye-delta transformer of LW single-phase and line-line ac faults with residual voltages of 0.8, 0.5, and 0 p.u. can be determined, as shown in Tables V and VI. Equivalent results can be found for single-phase and line-line ac faults on the other phases. If a different transformer winding arrangement is chosen, which does not introduce a phase shift between the LW and RLW voltages (unlike the star-delta arrangement), asymmetrical ac faults on the LW side would not affect the phase angles of the RLW voltages. Therefore, the ac fault ride-through strategies would only have to consider RLW voltages with depressed magnitudes but with zero phase shift as a result of the fault.

B. Maximum Valve Voltage During Nominal Operation
The maximum required valve voltage, when an arm is conducting the VW current, occurs at the start and end of "overlap," as seen in Fig. 5(b). By substituting (4)-(7) into (9) when g DSLx = 1, withV fund VWx = 1 p.u., V DC = 1 p.u., ωt = Φ OVx 2 rad, and Φ OVx = π 3 rad, the maximum valve voltage during nominal operation can be found as shown in (18). The 2 3 factor appears in (18) due to the change of base for the fundamental VW voltage magnitude from the nominal fundamental VW voltage magnitude to the dc voltage. The ratio between these two base voltages is defined by "sweet-spot" operation [12] V nom V max = 1 2 + 2 3

V. SINGLE-PHASE AC FAULT RIDE-THROUGH STRATEGY
The ride-through strategy for LW single-phase faults depends on one phase having a residual LW voltage of <0.75 p.u. or not; the reasoning for this is described in Section V-B. In order to illustrate the strategy, typical steady-state waveforms during phase "a" residual LW voltages of 0.8, 0.5, and 0 p.u. are shown in Sections V-A, V-B, and V-C, respectively. In order to illustrate the strategy, the reference dc circulating currents for phases "a," "b," and "c" are chosen to equal +0.1, −0.1, and 0 p.u., respectively (these currents sum to zero for the reason described in Section II-B), and the reference ac circulating current magnitudes for all phases are chosen to equal 0.2 p.u. These values for the reference dc and ac circulating currents are chosen to merely simplify the illustration and description of the strategy; they are actually calculated by the SM energy management block in Fig. 4, which is described in Section II-B. The reference circuiting current, which is the sum of reference dc and ac circulating currents, is set to zero during non"overlap" periods.   A. 0.8 p.u. Fault   Fig. 14 shows the phase "a" DS IGBT gate signals, the reference valve voltages, and the reference circulating current for a phase "a" 0.8 p.u. residual LW voltage. The corresponding waveforms for phases "b" and "c" are shown in Figs. 15 and 16, respectively.
In order that the fault does not cause the required valve voltage rating to increase, the phase with the largest (and unchanged) fundamental RLW voltage magnitude, which from Table V is phase "c" for this case, is used to calculate the ZPS VW magnitude by using (17) and the phase of this component is aligned to the phase "c" fundamental VW voltage, as shown in Fig. 17. Furthermore, "overlap" angular durations of 60 • are used for all phases and these periods are aligned relative to the phase "c" fundamental VW voltage zero-crossings. As for normal "extended-overlap" mode operation, "overlap" angular durations of 60 • are maintained, and therefore a smooth current component relating to dc side power is obtained. The "overlap" period alignment is achieved by setting the VW voltage angular displacement input for the DS gate signal generation block in Fig. 4 to the phase "c" VW voltage angular displacement.
The operation of phase "c" is still the same as the symmetrical fault case described in Section III because the ac circulating current of this phase equals +0.2 p.u. when v ref whereas the ac circulating current equals −0.2 p.u.
, as shown in Fig. 16. However, as the successive VW voltage zero-crossings during "overlap" between phase "a" and phase "c" and between phase "c" and phase "b" are not displaced by 60 • (see Table V), the ac circulating currents for phases "a" and "b" are not aligned with the corresponding reference valve voltage 0.5 p.u. crossings, as shown in Figs. 14 and 15. Yet, as the amount that the "overlap" periods are offset from the corresponding valve voltage 0.5 p.u. crossings is relatively small, applying the ac circulating currents during each "overlap" period on phases "a" and "b" as in the symmetrical fault case is still effective, although not optimal.
As the summed reference upper and lower valve voltages in each phase still equal 0.5 p.u. during "overlap," the dc circulating currents are still as effective as the symmetrical fault case during this fault, as well as during all other ac faults.

B. 0.5 p.u. Fault
The phase "a" and "b" waveforms for a phase "a" 0.5 p.u. residual LW voltage are shown in Figs. 18 and 19, respectively. As the magnitude and phase of the phase "c" RLW voltage is the same as that for a 0.8 p.u. fault (see Table V), the phase "c" waveforms are the same as those plotted in Fig. 16 and the ZPS VW voltage is the same as that plotted in Fig. 17 due to the reasons stated in Section V-A.
"Overlap" angular durations of 60 • are maintained for all phases. The phase "c" ac circulating current is still aligned with the 0.5 p.u. crossings of its valve voltages. The 0.5 p.u. crossings of the phase "a" and "b" valve voltages during "overlap" now occur at the start or end of "overlap," as seen in Figs. 18 and 19. Consequently, applying the corresponding ac circulating current during each "overlap" is now ineffective. However, as the VTA during "overlap" of the difference between the reference upper and lower arm valve voltages are equal in absolute value, but opposite in sign, for two successive "overlap" periods in phase "a" or in phase "b," the corresponding ac circulating current can be applied over two successive "overlaps" for phases "a" and "b," as seen in Figs. 18 and 19, to be effective. The functionality of the SM energy management block in Fig. 4 is expanded accordingly. During transients, the ac circulating current appears instantaneously in the dc pole currents (see Section II-B), but for phases "a" and "b," now sums to zero over two successive "overlap" periods in phase "a" or in phase "b," respectively, instead of over one "overlap" period, as previously.
The transition point between the normal ac circulating current operation mode, described in Section II-B and used in Section V-A, and the ac circulating current operation mode, used in this section, is selected to be when one phase has a LW voltage magnitude of 0.75 p.u. This point is halfway between all phases having a LW voltage magnitude of 1 p.u., where the VTA of the first and second halves of "overlap" are equal in absolute value but opposite in sign [see Fig. 6(a)], and one phase having an LW voltage magnitude of 0.5 p.u., where the VTA for two successive "overlap" periods of this phase are equal in absolute value but opposite in sign [see Fig. 18(b) or Fig. 19(b)].

C. 0 p.u. Fault
The phase "a" and "b" waveforms for a phase "a" 0 p.u. residual LW voltage are shown in Figs. 20 and 21, respectively. Due to the reasons stated in Section V-A, the phase "c" waveforms  The ride-through strategy during this fault is same as that described in Section V-B because one phase has a LW voltage between 0.75 and 0 p.u. However, during phase "a" and "b" "overlap" periods, V nom V max (see Section IV-B) is slightly exceeded by the reference valve voltages, as seen in Figs. 20(b) and 21(b). Yet, the maximum valve voltage (≈0.7 p.u.) only exceeds V nom V max by 5%.

VI. LINE-LINE AC FAULT RIDE-THROUGH STRATEGY
The ride-through strategy for LW line-line faults is described in this section. In order to simplify the illustration and description of the strategy, the typical waveforms have the same reference circulating currents as those given for single-phase faults in Section V.

A. 0.8 p.u. Fault
The phase "a," "b," and "c" waveforms for phase "a" and "b" 0.8 p.u. residual LW voltages are shown in Figs. 22-24, respectively. In order that the fault does not cause the required valve voltage rating to increase, the fundamental VW voltage magnitude of the phase which has most recently entered "overlap" is used to calculate the ZPS VW voltage magnitude by using (17) and the phase of this ZPS component is aligned to   the corresponding fundamental VW voltage. As the phase "b" fundamental VW voltage magnitude is the smallest in this case and as the phase of this component is unaffected by the fault (see Table VI), "overlap" periods of 60 • are used by phases "a" and "c" and these periods are aligned to the 0.5 p.u. crossings of the corresponding reference valve voltages, as seen in Figs. 22 and 24. Whereas, phase "b" has "overlap" periods during the remaining intervals of a fundamental period, as seen in Fig. 23. As the sum of the "overlap" periods across phases is maintained at 180 • , a smooth current component relating to dc side power is still obtained. The "overlap" period alignment is achieved by setting the VW voltage angular displacement input for the DS gate signal generation block in Fig. 4 to use the phase "a" and "c" VW voltage angular displacements for phases "a" and "c," respectively, with an "overlap" period input of 60 • , then the phase "b" "overlap" periods are the remaining intervals. Any net dc circulating current component, caused by operating phase-leg "b" with an unequal "overlap" period, is compensated for by the ac side power trimming controller (see Section II-B).
The ZPS VW voltage is shown in Fig. 25. If a reference valve voltage is going to exceed V nom V max during "overlap," the ZPS VW voltage, which is input to the valve voltage generation block in Fig. 4, is modified so that the reference valve voltage is now limited to V nom V max . The ride-through strategy described for this fault is also applicable to line-line ac faults with residual LW voltages all the way down to 0 p.u.

B. 0 p.u. Fault
The phase "a," "b," and "c," waveforms for phase "a" and "b" 0 p.u. residual LW voltages are shown in Figs. 26-28, respectively, and the ZPS VW voltage is shown in Fig. 29. The ride-through strategy during this fault is the same as that of a 0.8 p.u. fault. However, just before 0.002 s, for example, the phase "a" reference upper valve voltage slightly exceeds V nom V max during phase "a" "overlap" (see Fig. 26) because the phase "c" reference lower valve voltage is being limited to V nom V max by the ZPS VW voltage during phase "c" "overlap" occurring at the same time (see Fig. 28). Yet, the maximum valve voltage (≈0.7 p.u.) only exceeds V nom V max by 5%.

VII. EXPERIMENTAL RESULTS
The ac fault ride-through strategies presented in Sections III, V, and VI are experimentally validated by using the SSP, which   is described in detail in [29]. In summary, the experimental setup comprises the SSP, a OPAL-RT Technologies rapid prototyping control platform, and programmable power supplies for the ac and dc sides. There are three cabinets containing the SSP and control hardware, and these are pictured in Fig. 30. The main elements of the leftmost cabinet are three ac side single-phase transformers, six DSs, and six arm inductors. The middle cabinet contains 60 SMs (10 per arm). The rightmost cabinet houses the control hardware. Fig. 31(a) pictures the back of the middle cabinet showing backplane printed circuit boards (PCBs), and there are 12 in total (two per arm). Five SM PCBs are connected to each backplane PCB, by a plug and socket configuration, for ease of disconnection. Each SM PCB is connected to an IGBT module interface PCB, again by a plug and socket configuration. An unplugged SM PCB and its IGBT interface PCB are pictured in Fig. 31(b).   Fig. 1 illustrates the SSP schematic and shows voltage and current conventions. Positive active power indicates that the converter is inverting and positive reactive power indicates that current is lagging voltage. When operating the SSP in AAC "extended-overlap" mode with a dc voltage of 1 kV, the main parameters are given in Table VII. Data for the experimental results is captured by the OPAL-RT control platform at a sampling period of 135 µs and is plotted by MATLAB.

A. 0.5 p.u. Symmetrical AC Fault
When applying a 0.5 p.u. symmetrical fault to the ac supply voltages at rated power, the LW voltages and currents are shown in Fig. 32. The sudden depression in the voltages causes a spike in these currents, although protection limits are not exceeded. During the fault, the current magnitude is lower than prior to   the fault due to the change in the selected active and reactive power operating point, as shown by the LW powers in Fig. 33. Active power transmission is suspended and prefault reactive power compensation is maintained during the fault as priority is given to reactive power to provide ac voltage support in this article. However, the control strategy is fully adaptable to other combinations of active and reactive power priority. During the fault, as there is only a small LW active power (due to the power trim described in Section II-B to account for losses), but there is reactive power compensation, the LW voltages and currents are in quadrature. Fig. 34 shows the dc side voltages and currents. The sudden decrease in the dc side currents causes a ripple in the dc side voltages, which decays within ≈0.5 s. This ripple is determined  by the tuning of the dc voltage controller provided by the programmable power supply on the dc side, not by the converter, which is controlling active power. The additional harmonic content in the dc currents after applying fault is caused by the circulating currents required for SM energy management, as a result of the transient, not instantaneously canceling on the dc side (see Section II-B). Although, these currents do decay within ≈0.5 s. Additionally, experimental considerations, such as measurement errors and component tolerances, affect the cancelation. The harmonic content of the LW waveforms in Fig. 32 during faults is still however comparable to that during normal operation.
The valve currents are shown in Fig. 35. The fault causes a spike in these currents, although protection limits are not exceeded. As the LW voltages and currents are in quadrature during the fault, the VW voltages and currents are as well, if the relatively small phase angle introduced by ac side impedance is neglected. As DS operation is coupled to the VW voltage; the valve currents are therefore both positive and negative during the fault [also see Fig. 12(b)]. When a DS is required to open at the end of an "overlap" period, "zero-current" turn-OFF is achieved throughout by actually opening the DS when its valve current is negative, as illustrated by the zoomed phase "a" DS gate signal and valve current waveforms in Fig. 36. Fig. 37 shows the phase "a" maximum, mean, and minimum SM capacitor voltages. The fault causes the SM capacitor voltages to deviate from the set-point (100 V), but these voltages remain well within protection limits throughout. The phases "b" and "c" SM capacitor voltages also have a similar response.   Zoomed reference valve voltages are shown in Fig. 38 and the fundamental VW voltage magnitudes and reference ZPS component are shown in Fig. 39. During the fault, the reference ZPS component magnitude is ≈0 (see Table II). Consequently, the valve voltages are comparable to the ideal waveforms of Fig. 10(b) in Section III.

B. 0 p.u. Single-Phase and Line-Line AC Faults
When demanding the ac power supply to remove a phase "a" and phase "b" 0 p.u. fault, the LW voltages and currents are shown in Fig. 40. A limitation of the programmable ac  power supply is that when demanding a three-phase voltage with positive phase sequence (PPS), NPS, and ZPS components, only the PPS and NPS components are actually realized. However, as the wye-delta transformer would block the ZPS component, the three-phase voltage seen by the converter on the VW is still as desired. Another limitation of the ac power supply is that only one (or all) of the voltage magnitudes can be changed simultaneously, and, therefore, an interval of ≈50 ms between the two magnitude changes is observed. Consequently, a phase "a" and "b" 0 p.u. fault is observed initially up to the first LW voltage transition, followed by a phase "b" 0 p.u. fault up to the second LW voltage transition, and then the fault is fully removed. After the fault is removed, the LW currents ramp back to their prefault values over ≈200 ms due to the programmed power ramp rate used in this article.
The LW powers are shown in Fig. 41. During the fault, active power transmission is suspended, but reactive power compensation is continued to provide ac voltage support. As symmetrical LW currents are maintained, in the presence of an asymmetrical LW voltage, the LW powers both contain a twice fundamental frequency (100 Hz) ripple during the fault. After the fault has been removed, the prefault rated power is restored over ≈200 ms. Fig. 42 shows the dc side voltages and currents. There is a slight dip in the dc side voltages as the dc side currents return to their prefault values. Figs. 43 and 44 show the valve currents and the phase "a" SM capacitor voltages, respectively. The waveforms remain within protection limits throughout.      Zoomed reference valve voltages are shown in Fig. 45 and the fundamental VW voltages magnitudes and reference ZPS component are shown in Fig. 46. During the single-phase fault, these voltages are comparable to the corresponding waveforms presented in Section V-C and, during the line-line fault, are comparable to the corresponding waveforms presented in Section VI-B.

VIII. CONCLUSION
The AAC is a type of modular multilevel VSC that has been proposed for HVdc transmission applications. The AAC offers several benefits over the MMC, such as requiring typically 30%-40% fewer SMs with half the capacitance and providing improved attributes for handling dc side faults. A major benefit of the AAC "extended-overlap" mode, over the "short-overlap" mode, is that a bulky dc side passive filter is not required. As HVdc converters are required by regulations to stay connected to ac networks during ac faults and, depending on operator requirements and fault severity, the converters may be required to exchange reactive power with the ac network to provide ac voltage support and continue to transfer active power. Furthermore, prefault active power should be restored after the fault is removed and voltage or current protection should not be triggered at any point throughout the entire fault sequence. An additional requirement for modular multilevel VSCs during faults is to aim to ensure that the capacitor voltage of each SM still remains within normal operation limits so that the converter continues to operate properly and safely. The novel ride-through strategies presented in this article for symmetrical, single-phase, and line-line ac faults allow the AAC "extended-overlap" mode to help meet these requirements under all anticipated ac fault conditions. The strategies have been successfully experimentally validated on an SSP and steady-state and transient results for representative ac faults have been presented.

APPENDIX RELATIONSHIP BETWEEN LW AND RLW VOLTAGES
The phase-neutral LW voltages are related to the phase-neutral RLW voltages by (19). Given that LW voltages are defined by (20), the RLW voltages are then defined by (21) ⎡ Each of the RLW voltages in (21) can be expressed as a single phasor, as shown in (22), so that the magnitudes and phases are known directly. By using trigonometry to superimpose sine waves, the relationship between (21) and (22) is given by (23), where inverse tangent is four-quadrant ⎡ (23f)