Predicting SiC MOSFET Behavior Under Hard-Switching, Soft-Switching, and False Turn-On Conditions

Circuit-level analytical models for hard-switching, soft-switching, and <inline-formula><tex-math notation="LaTeX"> $dv/ dt$</tex-math></inline-formula>-induced false turn on of SiC MOSFETs and their experimental validation are described. The models include the high-frequency parasitic components in the circuit and enable fast, accurate simulation of the switching behavior using only datasheet parameters. To increase the accuracy of models, nonlinearities in the junction capacitances of the devices are incorporated by fitting their nonlinear curves to a simple equation. The numerical solutions of the analytical models provide more accurate prediction than an LTspice simulation with a threefold reduction in the simulation time. The analytical models are evaluated at 25 °C and 125 °C. The effect of snubber capacitors on the soft-switching waveforms is explained analytically and validated experimentally, which enables the techniques to be used to evaluate future soft-switching solutions. Finally, the <inline-formula><tex-math notation="LaTeX">$dv/ dt$</tex-math></inline-formula>-induced false turn-on conditions are predicted analytically and validated experimentally. It was observed that consideration of nonlinearities in the junction capacitances ensures accurate prediction of false turn on, and that the small shoot-through current due to false turn on can increase the switching loss by 8% for an off-state gate bias of −2 V.


I. INTRODUCTION
RANSFORMING the device level advances of SiC technology (lower on-state losses, lower parasitic capacitances and potentially higher switching frequencies) into smaller and more efficient converters present numerous challenges. One of the challenges is understanding and optimising the more rapid switching waveforms, including predicting and managing parasitic oscillations, switching losses and electromagnetic interference (EMI).
To understand the SiC MOSFET static and dynamic behaviour, several modelling approaches have been proposed, including semiconductor physics models [1] and behavioural models [2][3][4]. Most of the models are complex or poorly incorporate the circuit parasitic components, and so produce inaccurate circuit waveforms. Although the behavioural Spice model of [2] has a detailed model of the nonlinear Miller capacitor, C gd , it did not consider any parasitic inductance at the source or drain terminal. The model was extended in [3] considering the nonlinearity in all the device capacitances, however the approximation of drain to source capacitance, C ds , during the switching transients was complex as it was considered to fall exponentially for gate-source voltages around the threshold level. Recently, another PSpice based behavioural model of a SiC MOSFET module was reported in [4] which included a model for the nonlinear Miller capacitor, C gd dependent on the physical parameters of the MOSFET such as doping concentrations of the drift and JFET regions and the active chip area. The model also requires an estimation of the transition voltage near the knee point of the C gd -V ds curve to model C gd accurately.
Analytical modelling of the switching transients can be a good approach to understand the switching behaviour of SiC MOSFETs [5]. The models can then be extended to incorporate circuit parasitics, soft-switching of the power devices and also false turn on conditions. One of the key objectives of this work is to develop an analytical model to evaluate the SiC MOSFET's full switching behaviour.
Although the analysis of dv/dt-induced false turn on has been widely examined for low voltage Si MOSFETs [6][7][8], very little has been published [9] for the SiC MOSFET. Opposing views are apparent in the published literature on Si MOSFETs with regard to the impact of common source inductance on the false turn on. [6,7] suggest common source inductance reduces the chance of false turn on, whereas [8] suggests the opposite. [8] gives the most detailed analysis of a 80V Si MOSFET's false turn on by including almost all the parasitic components. However, the model did not consider the nonlinear characteristics of the device capacitances which are shown in this work to be critical for determining the dv/dtinduced false turn on of SiC MOSFETs. An  T analysis of temperature dependent losses associated with SiC MOSFET's false turn on was presented in [9] and compared with a Si IGBT. An analytical model was also introduced to predict only the gate to source voltage of the MOSFET and IGBT during false turn on, again considering only fixed device capacitances. However, the losses associated with the output capacitance of the devices were not quantified; these losses can be determined from the modelling approach presented in this paper. In this paper, Section II presents a theoretical overview of three different SiC MOSFET switching circuits. The associated waveforms establish the basis of the analytical models explained in Sections III and IV, which also show how the models can be implemented in MATLAB. Section V verifies the modelling approach for hard-switching, softswitching and dv/dt-induced false turn on conditions. Finally, Section VI draws conclusions.

A. Hard-switching
To investigate hard-switching the double-pulse test (DPT) circuit is used, Fig. 1 (a). The diagram includes the main circuit parasitics such as the MOSFET common source inductance, L s , drain inductance, L d , gate lead inductance, L g , parasitic capacitances of the MOSFET, C gs , C gd and C ds , diode and load inductor lumped parasitic capacitance, C ak , and the equivalent series resistance of the power loop, R s . Fig. 1 (b) shows simplified turn on waveforms for the MOSFET, including drain to source voltage, V ds , drain current, I d , gate to source voltage, V gs , Schottky diode voltage, V ak , and the diode current, I f .
V gs increases during t 0 -t 1 in an exponential manner as the gate current charges the MOSFET input capacitances, C gs and C gd . V gs reaches the threshold level, V th at t 1 and I d starts to increase. At the same time, diode current, I f also starts to fall from the load current level, I dd and at time t 2 , the current commutation between the diode and MOSFET finishes. During this sub-period, t 1 -t 2 , due to the voltage drop, V ls , across L d and L s , V ds reduces from the input DC voltage, V dd .
At time t 2 , V ds starts to fall as the voltage starts to increase across the diode parasitic capacitor, C ak . The MOSFET current I d increases beyond the load current level due to the charging current of C ak until V ak reaches the level V dd ̶ V ls at time t 3 . At this point, V ds reaches its on-state voltage level, V ds(on) . After t 3 , I d rises slightly then starts to reduce as the energy in the stray inductances transfers to C ak in a resonant manner. This resonance continues until all the resonating energy is dissipated by the stray resistance, R s , of the circuit. Finally, the drain current is equal to the load current, I dd , the diode voltage, V ak becomes equal to the DC voltage, V dd , and V gs is equal to the gate supply voltage, V gg . The switching transient at turn off follows a reverse process to that seen at turn on. The subintervals for turn off are the same as those at turn on but occur in the reverse order.

B. Soft-switching
To facilitate the soft-switching test, a different arrangement of the DPT circuit, shown in Fig. 2(a), was used where C1 and C2 are large voltage dividing capacitors. Two snubber capacitors, C s1 and C s2 are added across Q1 and Q2 to reduce the MOSFET turn off losses and control the dv/dt. The total capacitance across the devices is therefore the sum of the snubber capacitor and the device output capacitances. The capacitances are charged and discharged in a lossless manner as Q1 and Q2 turn off ( Fig. 2(b)). During the turn off instant of the device under test (DUT), Q2, C s1 and C s2 slow down the voltage transient to reduce the turn off losses. Energy is stored in C s2 whilst C s1 is discharged. The energy stored by C s2 is recovered into the conversion process when Q1 turns off. Fig. 3(a) shows the soft-switching circuit during the turn off of the DUT, Q2. Here I c1 and I c2 are the currents flowing through the snubber capacitors C s1 and C s2 , respectively. The turn off waveforms are shown in Fig 3 (b).
The gate to source voltage, V gs decreases during t 0 '-t 1 ' in an exponential manner as the gate current discharges the MOSFET input capacitances, C gs and C gd . V gs reaches the Miller level, V mil at t 1 ', V ds starts to increase and I d starts to decrease. Due to the snubber capacitors, V ds increases gradually while I d falls, reaching zero at t 2 ' as V gs reaches its threshold level, V th . In this sub-period I dd commutates to the snubber capacitors.
During the sub-period t 2 '-t 3 ' I dd is shared equally by the two snubber branches. Due to the parasitic inductance in the current paths, both I c1 and I c2 will be oscillatory. Towards the end of the t 2 '-t 3 ' sub-period V ds will reach V dd and the upper device will start to conduct (I d1 ) terminating the snubber branch currents. After t 3 ', the circuit capacitances and inductances will continue to resonate until a steady state is reached when the upper device current, I d1 equals the load current, I dd , I c1 and I c2 become zero, and V gs equals the negative bias level of V ggl .

C. dv/dt-induced false turn on
To investigate the dv/dt-induced false turn on, the DPT circuit in Section II.B was used with some minor modifications. In Fig. 2, the inductor, L, was connected to the ground, the snubber capacitors were removed and the DUT was held off by setting a negative gate bias on Q2. A single pulse was applied to the gate of Q1 and as the device turned on a high dv/dt was imposed across Q2 which created a displacement current through the output capacitors of Q2. Depending on the speed at which Q1 turns on, the gate resistance of Q2, R g2 , the negative gate bias, V ggl , and the stray inductances associated with Q2, a false turn on of Q2 could happen if the induced gate to source voltage, V gs2 , exceeds the threshold level. The presence of the load inductor ensures that the initial voltage across Q2 is zero, however the inductor current remains virtually zero due to its large inductance (460 µH) and the component is neglected in the analysis. It was assumed that the effect of inductor current on the dv/dt is negligible compared with the effect of gate resistances and device capacitances and the validity of this assumption was confirmed by the experimental measurements in Section V. Also the current sensed at the source of Q2 by the shunt resistance, R shunt , will include the displacement current through the output capacitor of Q2 and its channel current if false turn on happens.
The false turn on process is explained in Fig. 4 using the equivalent circuit in Fig. 4 (a). During t 0 ''-t 1 '', Q1 remains turned off as V gs < V th . At t 1 '', the current starts to flow in the channel of Q1 as well as in the drain of Q2 (I d ) while the output capacitance of Q1 discharges and the output capacitance of Q2 is charged. The induced voltage across L s2 initially reduces V gs2 , but V gs2 then increases due to the Miller current flowing through R g2 . If V gs2 crosses the threshold level, Q2 turns on and I d increases. At t 2 '', Q1 becomes fully on and V ds2 reaches the DC voltage, V dd , and the dv/dt across Q2 starts to decrease. During the rest of sub-period t 2 ''-t 3 '' V gs2 gradually decreases to V ggl while the oscillations in V ds2 and I d are damped by the resistance of the circuit, R s .

TRANSIENTS
Modelling the SiC MOSFET turn on and turn off transients requires the solution of four equivalent circuits corresponding to the four distinct stages of each transient. The modelling approach is similar to the published Si-MOSFET analytical models [10,11], but the difference is the incorporation of the major circuit parasitic components in all of the transient stages. Also no assumptions are used in the model to predict the voltage transitions between the equivalent circuits. The 'ode45' differential equation solver was used in MATLAB to solve the state equations for each sub-period. The final values from one sub-period form the initial conditions for the next sub-period. The equivalent circuits for the turn on and turn off transient states are shown in Fig. 5. Here, L d is the sum of the inductances of the MOSFET drain lead, L drain , PCB current paths, L pcb , diode leads, L lead , and current shunt resistor, L shunt . Four state variables, V gs , V ds , I d and İ d (rate of change of drain current), were considered and were solved using four state space equations. A step gate pulse from V ggl to V gg was used to initiate the turn on transient. The other two inputs were the supply voltage, V dd and load current, I dd . The four sub-periods during the turn on transient correspond to (i) turn on delay, (ii) drain current rise, (iii) drain to source voltage fall and (iv) ringing stages. The gate inductance, L g was neglected because it is small (around one fourth) compared with the power loop inductance, L d +L s , and the validity of this assumption was confirmed by the experimental measurements in Section V.
A. Turn on model A step gate pulse from V ggl to V gg initiates turn on which drives the solution of the turn on transient model (V ggl < 0).
Sub-period 1: (t 0 -t 1 ) (turn on delay) After the gate pulse is applied, the gate current charges the MOSFET input capacitors C gs and C gd . The MOSFET stays off until V gs reaches V th and the load current, I dd circulates through the Schottky diode. The drain current is zero and the drain to source voltage is equal to the DC link voltage, V dd in this subperiod. From equations (1)-(3) the state equations (4)-(5) for this sub-period can be found where, I d = 0 and C iss = C gs + C gd . After solving state equations (4)-(5) in MATLAB using V g_in =V gg and the initial conditions, V gs (0) = V ggl and I g (0) = 0, V gs and I g for this sub-period can be found. The turn on delay, t 1 ̶ t 0 , is the time required for V gs to reach V th from V ggl .
Sub-period 2: (t 1 -t 2 ) (current rise time) The current commutation between the diode and MOSFET happens in this stage. As the MOSFET is in the saturation region its channel current will be directly proportional to (V gs ̶ V th ). V ds decreases in this stage because of the di/dt induced voltages across L s and L d as shown in (6).
The drain current can be found by combining the channel current with the MOSFET output capacitance current as shown in (7) where C oss = C ds + C gd .
To simplify the model the impact of the gate current, I g , on the common source inductance, L s was neglected assuming I g is much smaller than the drain current, The state equations (A1) for this sub-period are derived using (2)-(3) and (6)- (8) and are shown in the Appendix. The current rise time, t 2 ̶ t 1 is the time required for V gs to reach V mil from V th , where, V mil = I dd /g m +V th and g m is the transconductance of the MOSFET. The drain current will reach the load current level at the end of this sub-period.

Sub-period 3: (t 2 -t 3 ) (Voltage fall time)
The voltage V ak across the Schottky diode capacitance C ak is expressed as (9) and V ds can be expressed as (10) for this subperiod. The state equations (A2) for this sub-period are derived using (2)-(3) and (7)- (10) and are shown in the Appendix. The voltage fall time, t 3 ̶ t 2 is the time required for V ds to reach V ds(on) from V ds (t 2 ).
Sub-period 4: (t 3 -t 4 ) (Ringing period) As the MOSFET is now in the ohmic region, the drain current can be expressed as (11). The state equations (A3) for this sub-period, derived using (2)-(3) and (8)- (11), are shown in the Appendix. High frequency parasitic inductances are considered in this sub-period as well as shown in (10). The time for this sub-period, t 4 ̶ t 3 is approximated by the time required for V gs to reach V gg from V gs (t 3 ).
Model implementation Fig. 6 shows a summary of the turn on solution process in MATLAB. The state equations are solved using the parameters and parasitic values shown in Table I (Section IV.C). When solving (A2) for sub-period 3, the nonlinearities in junction capacitances were considered. These voltage dependent parasitic capacitances of the MOSFET (C gd , C iss and C oss ) and the Schottky diode (C ak ) were modelled by fitting their datasheet curves to (12) which is based on the equation typically used for low voltage silicon MOSFETs [10]. C 0v and C hv are the low voltage and high voltage capacitance values used to calculate the curve fitting coefficients x and C j . The C hv term was included in (12) to achieve acceptable fitting of the variable capacitance curve over the wide voltage range of the 1200V SiC MOSFETs.
The linear state equations (A2) were solved in a loop with the junction capacitance values being updated after every ten time steps until V ds reached V ds(on) . Then, (A3) was solved for sub-period 4, using the low voltage junction capacitance values, until V gs reached V gg when the simulation finally ends. Datasheet values of the devices' capacitances [12][13][14] were compared with the fitted model, equation (12) in Fig. 7 for a SiC MOSFET, C2M0080120D and two SiC Schottky diodes, Cree C4D10120D and ROHM SCS230KE2. Fig. 7 shows that the variation of the devices' capacitances is well captured. The program updates the capacitor values around 100 times during a 600V, 20A switching transient which was judged to provide a good balance between accuracy and speed of simulation.  C. Turn off model A gate voltage transition from V gg to V ggl initiates the turn off sequence. The four turn-off sub-periods, Fig. 5, are identical to the turn-on sub-periods but occur in reverse order. The state equations can be derived in a similar manner. After the negative gate pulse is applied, the MOSFET input capacitors C gs and C gd begin to discharge. (4) and (5) are the state equations for the sub-period 1 (turn off delay) and the state variables can be solved using V g_in = V ggl and the initial conditions, V gs (0) = V gg and I g (0)=0. The state equations for sub-periods 2 and 3 will be exactly the same as the corresponding turn on equations, (A2) and (A1), respectively. In sub-period 4, the MOSFET is in the cut-off region and the MOSFET output capacitor, C oss resonates with the stray inductances of the circuit. The drain current can be expressed as (13). The state equations (A4) for this sub-period are derived using (2)-(3), (6), (8) and (13) and are shown in the Appendix.

Sub-period 4': (t 3 't 4 ') (Ringing period)
Because the diode on state resistance, R d was considered, one additional state variable V s1 has to be solved in this subperiod. The state equations (A7) are derived using (2) (7)-(11) of the previously described hard-switching model in Section III.A are used to derive (A8) and (A9). When solving (A8) all the device parasitic capacitances are modelled by fitting their nonlinear curves to equation (12) as explained in Section III.B.

C. Numerical solution of analytical model
The analytical models were solved in MATLAB using datasheet information for R ds , g m , R d , V F , package inductances and device capacitances [12][13][14], and measured values from the PCB layout, Table I. The power circuit parasitic values were measured using a precision impedance analyser, Agilent 4294A. The resistance of the power loop, R s is the sum of the AC resistances of current shunt resistor, R shunt , PCB current paths, R PCB , MOSFET and diode resistances (R ds , R d and R leads ). The inter-winding parasitic capacitance of the load inductor, C L and its high frequency AC resistance, R L were included in the model in the ringing sub-periods.

V. SIMULATION AND EXPERIMENTAL RESULTS
A 600V, 20A double-pulse test (DPT) circuit shown in Fig. 8 was considered. A Cree SiC MOSFET gate driver circuit, CRD-001 was used. T&M Research's high-bandwidth (2 GHz) current shunt resistor, SDN-414-01 was used to measure the source current. LeCroy high-voltage-highbandwidth passive probes, PPE2KV (400 MHz) and PP008 (500 MHz) were used to measure V ds and V gs respectively. A de-skew calibration test was performed in the Teledyne LeCroy 400 MHz Wave Runner 44Xi-A oscilloscope to compensate the different propagation delays between V ds and I d . The connection of the load inductor can be changed to enable hard-switching, soft-switching and false turn on tests to be performed using the same circuit for fair comparison.
The DPT circuits were also simulated in LTspice using the manufacturers' Spice models of the SiC MOSFET (C2M0080120D library beta version) and Schottky diodes (C4D10120D-11/2014 version and SCS230KE2-02/2013 version). A time step of 0.01ns was selected for both the numerical calculation of the model and the LTspice simulation as the SiC MOSFET switching transient times are around tens of ns.

A. Hard-switching
Experimental, calculated and LTspice simulation transients for hard switching operation at 600V 20A are shown in Fig. 9 and 10 for two different Schottky diodes when the junction temperature of the MOSFET (T j ) was around 25°C. The V ds and V gs waveforms include the voltages across the device package inductances and resistances. The experimental dV ds /dt was 31 kV/µs at turn on and 46 kV/µs at turn off. The experimental di/dt was 1.5 kA/µs at turn on and 1.1 kA/µs at turn off. In both figures, the calculated and LTspice simulated voltage and current transients showed a good match with the experimental results. The V ds and I ds waveforms are first multiplied to get P on and P off and then integrated to calculate the switching energy losses. The losses from the experiments are summarised in Table II. It is evident that compared to the LTspice models the analytical models gave a better switching loss estimation (less than 10% error in most cases). The maximum errors from the analytical models were around 13% for individual losses and around 3% for the total switching losses. Whereas, the maximum errors from the LTspice simulations were around 47% for individual losses and around 26% for the total switching losses (with the ROHM diode). The maximum errors from the LTspice simulations with the Cree diode were around 11% for both the individual losses and the total switching losses. The DPT circuit was also tested using higher and lower gate resistances and lower supply voltages; the percentage errors in the predicted switching losses were found to be similar to those in Fig. 9 and 10. Both experimental and LTspice turn off losses include the energy stored in the device output capacitance and other circuit stray capacitances, which eventually is dissipated during the turn on transient. Ideally this loss should be part of the turn on loss, however due to practical limitations it is almost impossible to measure the MOSFET channel current. Therefore, this loss is normally considered to be a part of the turn off loss. The analytical model enables the actual turn on and turn off losses to be calculated from the modelled channel current of the MOSFET and V ds .
The analytical modelling results considering constant device capacitances as assumed for Si MOSFETs in [10,11] have a very poor correlation with the experimental results. Using the SiC MOSFET datasheet, [12], C gd was calculated from the Miller charge, Q gd assuming linear drain to source voltage transitions and C oss was calculated from the C oss stored energy. Diode capacitances C ak were calculated using the total capacitive charge from their respective datasheets [13,14]. The results are omitted in Fig. 9 and 10 for clarity, but the switching losses are listed in Table II which showed as high as 154% error in estimating the individual losses and 69% error in the total switching losses. The advantage of the proposed analytical model over the LTspice model is a three times reduction in calculation time, a single turn on transient takes 0.6s to complete on an Intel Core i7 3.4 GHz computer. Therefore, the model has the potential to be used in a design optimization program where increasing the speed of the simulation is one of the key challenges because of the numerous iterations within the program. Also the effect of temperature on the switching transients can be evaluated easily by changing the temperature dependent parameters in Table I. However, the modelling of ringing in the different waveforms is still limited in both the analytical and LTspice models as it can be seen that the measured results are more oscillatory than the predictions ( Fig. 9 and 10). Additional parasitic elements such as drain to gate external parasitic capacitance and accurate approximation of the high frequency AC inductance of the power loop may need to be considered for better modelling of the ringing.
Experimental, calculated and LTspice simulation transients and switching energy losses for hard switching operation with the Cree diode at higher MOSFET junction temperature, Tj=125°C are shown in Fig. 11 and Fig. 12. Fig. 11 compares the calculated and LTspice simulation transients with the experiment transients for high-temperature DPT operation at 600V, 20A. The temperature dependent parameters V th , g m and R ds were updated in the analytical model and the manufacturers' high temperature Spice model of the SiC MOSFET was used in LTspice. Fig. 12 compares the calculated and LTspice simulated switching energy losses with the experimental losses for a wide range of load currents (8A to 20A) at both T j = 25°C and 125°C with V dd fixed at 600V. From both Fig. 11 and 12 it is clear that the calculated and LTspice simulated transients and switching energy losses show an excellent match with the experimental results. As expected, the turn on losses are reduced and the turn off losses are increased with the higher junction temperature (consistent with the MOSFET datasheet [12]). In most cases errors from the analytical models were less than 10% and from the LTspice models were less than 13% (similar to the 25°C results). However, the modelling of the ringing becomes more challenging at higher temperature. Comparing the I d waveforms at turn off between Fig.11(b) and Fig. 9(b) it is clear that the turn off oscillation is more heavily damped, which was attributed to the increased MOSFET-lead resistances at higher temperature.

B. Soft-switching
The DPT circuit was tested in the soft-switching configuration using identical SiC MOSFETs as used in the hard-switching tests as the upper and lower leg devices. Fig. 13 shows experimental, analytical and simulation results of soft-switching at 600V, 13A and 20A. Comparing Fig. 13(b) with Fig. 9, the snubber circuit has reduced both the dv/dt by a factor of seven and the frequency of oscillations by a factor of three. Here, the analytical model predicts much more ringing in the V gs waveforms which is attributed to the high frequency AC resistance of the upper MOSFETconnections (Q1) which needs to be predicted more accurately to enable a better match. The analytical model also enables the calculation of the small turn off loss of 4 µJ and 10 µJ for 13A and 20A operations respectively by separating the MOSFET drain current, I d , from the shunt resistor current, I d +I c2 . The turn on losses will be approximately zero as the MOSFET turns on with zero voltage across it because of its body diode conduction. Therefore, for 20A soft-switching operation around 92% of the hard-switching energy was saved during turn off making the total soft-switching loss reduction 97% compared to the hard-switching conditions.

C. dv/dt-induced false turn on
The test circuit was operated with two Cree SiC MOSFETs in the phase-leg to investigate false turn on at different conditions by changing the gate resistances and negative gatebias voltages. The analytical model accurately predicted the false turn on conditions by calculating the voltage across the gate to source capacitance (C gs2 ) of the lower MOSFET during the turn-on transient of the upper device. Fig. 14 (a) shows the experimental and analytical results for the lower MOSFET (Q2) while the upper MOSFET (Q1) turns on at 600V with a speed of 40 kV/µs causing false turn on of the bottom device. The experimental V gs2 does not give an accurate indication of false turn on as it consists of voltages across the internal gate resistance (R gint ) of the MOSFET, common source inductance (L s2 ) and C gs2 . Fig. 14 (a) also shows that analytical results considering constant device capacitances, as assumed in [8,9], have a poor correlation with the experimental results. This again confirms the importance of including the nonlinearity in the device capacitances. To check the efficacy of the modelling approach two specific gate resistances were selected for the upper and lower MOSFET, 34.6Ω and 24.6Ω, respectively. Now the negative gate bias, V ggl was changed gradually to find a voltage where V gs2 , the gate-source voltage of the lower MOSFET crosses the threshold level. It was found that for a negative gate bias of 1.2V false turn on happens for the lower MOSFET ( Fig. 14(b)). Analytical modelling also predicts a similar value for V ggl during the false turn on of the lower MOSFET. The analytical modelling results considering non-linear and constant device capacitances are again compared in Fig. 15 and Fig. 16. Considering the upper MOSFET turning on at 600V with a gate resistance (R g1 ) of 11.27Ω, Fig. 15 shows the combinations of lower MOSFET gate resistance, R g2 (varied from 4.6Ω to 30Ω) and V ggl (varied from 0V to -8V) which cause false turn on of the lower MOSFET. In one analytical model the MOSFET device capacitances were nonlinear ( Fig. 15(a)) and in the other model the MOSFET device capacitances were taken as average values (Fig. 15(b)). It is clear that when V ggl is between -2.5V to -8V, the fixed capacitance based model gives inaccurate prediction of false turn on. Also in the non-linear capacitance based model the chance of shoot through reduces with the increased R g2 because the high common source inductance, L s2 is dominating the shoot through mechanism [8]. Fig. 16 shows a similar analysis when both of the gate resistances are equal, R g1 = R g2 . Comparing Fig. 16 (a) with the Fig. 16 (b), when V ggl is between -1.7V to -8V, the fixed capacitance based model gives inaccurate prediction of false turn on. The shoot through current due to false turn on increases the switching loss of the bottom and top devices by around 20 µJ and 7 µJ, respectively, because of the increased device current. However, 27 µJ of energy is stored in the bottom device and the circuit parasitic capacitances (Fig. 14 (b)). Ideally this energy should not be considered as dv/dt-induced loss as it is part of total stored capacitive energy in the device and circuit parasitic capacitances. The total dv/dt-induced loss was the same (27 µJ) as for the experiment in Fig. 14 (a) which makes the additional loss 8% of the total switching loss of the MOSFET (considering 600V, 20A operation with the Cree diode and assuming false turn on loss is independent of the load current).

VI. CONCLUSIONS
The analytical model presented in the paper, and validated experimentally can be used to enable rapid and accurate evaluation of circuit waveforms, device switching losses and dv/dt-induced false turn on events. The analytical model uses only datasheet parameters, so the impact on circuit operation and switching losses of SiC MOSFETs or diodes at different temperatures with different snubber capacitor values and circuit parasitics can be evaluated. In comparison with established Si-MOSFET analytical models, this paper shows how those models must be enhanced and refined in order to represent accurately the behaviour of SiC MOSFETs.
The paper also describes the analytical and experimental evaluation of the impact of soft-switching on the MOSFET switching loss, dv/dt and parasitic ringing, which provides an understanding of the benefits of soft-switching in very high speed SiC circuits. The switching loss was reduced by 97% with soft-switching along with an 86% reduction in dv/dt during the switching transients, which is likely to reduce significantly the EMI signature and unwanted parasitic events such as dv/dt-induced false turn on. These improvements suggest that the use of soft-switching techniques in high speed SiC MOSFET based converters could offer significant performance benefits.
It has been shown that false turn on can increase switching energy loss of the MOSFET but not as significantly as reported in some recent papers. For example in the results reported here almost half of the switching energy losses associated with the false turn on of the devices is actually the stored capacitive energy in the device and circuit parasitic capacitances -conventionally it was included in the total false turn on related losses.
Finally, it has been shown that to predict the SiC MOSFET's switching behaviour accurately it is important to model the non-linear device capacitances. If these capacitances are assumed fixed, inaccurate circuit waveforms will result and there will be serious errors in the estimation of losses, and shoot through events. Therefore, it is recommended that the Spice model of a SiC MOSFET or Schottky diode should include a good model of device capacitances for better prediction of its behaviour.