A Novel Repetitive Controller Assisted Phase-Locked Loop with Self-Learning Disturbance Rejection Capability for Three-Phase Grids

The synchronization between the power grid and distributed power sources is a crucial issue in the concept of smart grids. For tracking the real-time frequency and phase of three-phase grids, phase-locked loop (PLL) technology is commonly used. Many existing PLLs with enhanced disturbance/harmonic rejection capabilities, either fail to maintain fast response or are not adaptive to grid frequency variations or have high computational complexity. This article, therefore, proposes a low computational burden repetitive controller (RC) assisted PLL (RCA-PLL) that is not only effective on harmonic rejection but also has remarkable steady-state performance while maintaining fast dynamic. Moreover, the proposed PLL is adaptive to variable frequency conditions and can self-learn the harmonics to be canceled. The disturbance/harmonic rejection capabilities together with dynamic and steady-state performances of the RCA-PLL have been highlighted in this article. The proposed approach is also experimentally compared to the synchronous rotation frame PLL (SRF-PLL) and the steady-state linear Kalman filter PLL (SSLKF-PLL), considering the effect of harmonics from the grid-connected converters, unbalances, sensor scaling errors, dc offsets, grid frequency variations, and phase jumps. The computational burden of the RCA-PLL is also minimized, achieving an experimental execution time of only $12~\mu \text{s}$ .


I. INTRODUCTION
Accurate real-time phase tracking of power grids is required for the synchronization of distributed power sources and their integration in the modern concept of smart grids. With more and more power electronics interfaced to the power networks, issues such as harmonics introduced by power converters, load unbalances, as well as measurement scaling error and d.c. offsets, produce periodic disturbances and degrade the accuracy of the phase tracking using a traditional phase-locked loop (PLL).
Vast varieties of three-phase PLLs have been proposed in literature. Although, there is no clear classification yet, authors in [1] have categorized three-phase PLLs according to their operating coordinates. We therefore have PLLs in natural abc coordinates (such as the zero crossing method [2]), in stationary αβ coordinates (such as the second order generalized integrator (SOGI) PLL [3]), and in rotating dq coordinates (as the synchronous rotation frame (SRF) PLL [4], the dq frame filter based PLL [5]). Authors in [6] have compared the SRF-PLL and some PLLs in the other two categories under conditions such as harmonics, voltage dips, and grid frequency variation; the SRF-PLL results as the simplest method that can sufficiently perform in all the test conditions. However, it needs to be dynamically slow to properly attenuate the harmonics and it provides poor performance on phase jumps [7].
In addition, as the SRF-PLL is based on a second-order model, it cannot track a frequency ramp without introducing a phase error. To solve such issues, a novel PLL structure, based on a third-order model Steady-State Linear Kalman Filter (SSLKF-PLL), has been originally proposed in [8] to mitigate the speed noise measurement in electrical drives. Such a technique has then been extended to the grid phase estimation for the first time in [9]. A third-order model has been successively employed in the type-3 SRF-PLL [10], which recently has been demonstrated to produce equivalent results to SSLKF-PLL [11].
A partial classification and a performance comparison of PLLs with enhanced filtering capabilities have been presented in [12]. Many papers have been published aiming at the enhancement of PLLs' disturbance rejection capability. For example, the notch filter (NF) based PLL [13] is fast, with strong filtering capability and adaptive to grid frequency variations. However, the disturbance due to d.c. sensor offsets have been not considered in [13]. Other advanced PLLs, such as the multiple-complex coefficient-filter (MCCF) PLL [14] and the multiple delayed signal cancellation (MDSC) PLL [15], are adaptive to grid frequency variations and can reject quickly all the aforementioned disturbances. However, their computational burden increases as the number of harmonics to cancel increases. Therefore, pre-knowledge of the harmonic pattern is required to reduce the unnecessary computational burden.
It seems that the requirements of effective disturbance rejection, fast dynamics, adaptive to grid frequency variations and a low computational burden are difficult to achieve all at the same time. A good balance between all these requirements has been achieved by using the SSLKF-PLL [9,16,17], which has been compared with the Discrete Fourier Transform (DFT) based PLL [18] in [19], showing superior performances in all the tested conditions. The aim of this paper is to design a PLL that fulfils all the above-mentioned requirements at the same time. As a result, a novel Repetitive Controller Assisted SRF-PLL (RCA-PLL) is proposed in this paper. Particularly, it can self-learn the grid harmonic pattern online while its computational burden does not increase if more target harmonics occur. Therefore, a benefit of the RCA-PLL is represented by the minimized computational effort, leading to an execution time of around 12μs, which is the same as the SSLKF-PLL.
Although RC has been used for PLLs in [20], its usage is more similar to a band-pass filter that mitigates the odd harmonics; furthermore, it is structurally very different from the traditional RC initially proposed by the authors in [21]. Moreover, to make the RC adaptive to grid frequency variation, the RC employed in the proposed solution is upgraded using a Lagrange fractional filter. Besides, fast dynamic of the SRF-PLL is maintained since the RC only works on harmonic rejections, while the SRF-PLL is responsible for the dynamic response.
This paper is organized as follows: the influences of harmonics, unbalances/sensor scaling errors and d.c. offsets in the grid voltages on its dq axis components will be analyzed in Section II. The RCA-PLL will be described in Section III. The SSLKF-PLL will be reviewed in Section IV. An experimental comparison among the RCA-PLL, the basic SRF-PLL and the SSLKF-PLL will be illustrated in Section V. The conclusions will be given in Section VI.

II. MAKING FULL USE OF THE PARK TRANSFORMATION
One way to obtain better performances of a PLL is to filter the distortions in the three-phase voltages measurements. However, the analysis on the Park transformation results in the following subsections, performed under a variety of grid anomalies as well as considering the errors introduced by the measurements conditioning interfaces, shows that such issues can be solved without filtering the three-phase voltages.
The Clarke Transformation and the Park Transformation matrices are defined as in (1).

A. Harmonics distortion
If a balanced three-phase system Uabc is polluted with the n th harmonic, it is widely known that the (n-1) th and (n+1) th harmonics will be generated in Udq after the Clarke and Park Transformations.
B. Negative sequence due to unbalances or sensor scaling error A balanced grid only has positive sequence voltages. If any unbalances occur, negative sequence voltages will arise. Assuming the amplitudes of the positive, negative and zero sequences are U1, U2 and U0, respectively, the resultant dq axis components generated by the negative sequence voltages are as in (2). As shown, a second harmonic in Uq is generated by the negative sequence voltages. Whereas, for the positive and zero sequences, there are no effects on Uq as in (3) and (4).
C. Offset error d.c. offsets in three-phase voltages may occur due to reasons such as sensors offset errors or mismatch in the signal conditioning circuits. Assuming the offsets are x, y and z for the three phases, the resultant dq axis voltages are as in (5). As shown, d.c. offsets produce first order harmonics in the dq axis voltages.
Summarizing the analysis results, it can be noticed that, the d.c. value of the q axis voltage is always zero once the θ used in the Park Transformation matches the real phase θ of the threephase voltages. Therefore, to make the PLL work with the distorted three-phase voltages, the key is to control the d.c. value of Uq to zero.
The results also indicate that, when the grid voltage is distorted, ripple may appear in the frequency and phase identified by the SRF-PLL in Fig. 1, the mean value of the frequency still remains accurate since the Proportional-Integrator (PI) controller will bring the d.c. value of Uq to zero. Hence, to make full use of this characteristic, the average value of the frequency has been used in the intended harmonic compensation scheme. The symbols in Fig. 1 will be defined later in Section III.

III. THE PROPOSED RCA-PLL
A novel Repetitive Controller Assisted PLL (RCA-PLL), whose block diagram is shown in Fig. 2, is proposed.  Fig. 2(a), RC denotes the repetitive controller, ω0=100π is the initial value for the output angular speed ω of the PI. The input of the PLL are the three-phase voltages Uabc, the outputs are the tracked frequency fpll and the tracked phase θpll. In Fig.  3(b), MAF denotes the moving average filter, D is the fractional number of delay calculated from the ratio between the sampling frequency fs (which equals 20 kHz in this paper) and the average tracked frequency f̅ pll. The fractional delay z -D is implemented using a 6 th order Lagrange fractional delay filter. Qrc is namely the forgetting factor of the RC, Grc is the gain of the RC. TD denotes the transient detector: once a transient is detected, the input and output of the RC will be set to zero for 0.01s (i.e. half a cycle for a 50 Hz system).
The working principles of the RCA-PLL operating at fixed grid frequency have been introduced in [22], whilst in this paper a modified structure of the RCA-PLL is investigated for the first time in order to adapt the operation to grid frequency variations.
A flowchart of the RCA-PLL for the (k+1) th interval is illustrated in Fig. 3. Considering one sampling period of computational delay, only the tracked frequency fpll and Uq err of the previous sampling period are available in the (k+1) th interval. Any sudden step changes of more than 8 Hz in fpll, are detected to properly disable the RC, otherwise a wrong computation action may be generated due to the transients in the frequency tracking. More explanations on how the RC improves the tracking performance when harmonics in Uq present will be explained later in the Zero Error Tracking Proof section in III-D.

A. Transfer functions
The transfer fucntion of the MAFs are as in (6), where, window sizes of the two MAFs are both chosen to be 400 because when the fundamental frequency is 50 Hz, there are 400 samples each cycle if fix the sampling frequency to 20 kHz. According to the ENTSO-e standard [23], the fundamental frequency should be regulated in the range 49.5 ~ 50.5 Hz. The fractional number of delay D is limited accordingly from 396 to 404.1 (i.e. 20kHz/50.5Hz to 20kHz/49.5Hz). The transfer function of the RC is therefore as in (7).
As shown in Fig. 3, the fractional number D is updated in every sampling interval according to the newest tracked grid frequency. The fractional delay z -D is implemented using a Lagrange fractional delay filter. Denoting with Di and Df respectively the integer portion and the fractional part of the number D, i.e. D=Di+Df, 0<Df<1, the memq err (k-D) in Fig. 2(b) and Fig. 3 can be calculated as in (8) and (9), where, the order n is chosen to be 6. As shown in Fig. 4, the value of memq err at tk-D is interpolated using other seven memorized data at tk-Di-6, The transfer function of the PI controller is expressed as (10): where kp is the proportional gain and ki is the integral gain. Ts is the sampling period, and Ts=1/fs. As given in (7) and (10), there are four parameters to tune in the RCA-PLL, i.e. the gain Grc and the forgetting factor Qrc for the RC, and the gains kp, ki for the PI controller. These four parameters can be chosen according to stability criteria. Before analyzing the stability of the system, it is worth deriving the equivalent diagram for the RCA-PLL.

B. Equivalent Diagram and Working
Principle of the RCA-PLL Given the balanced and purely sinusoidal three-phase voltages Uabc as defined in (11), where, U1 denotes the peak value of the positive sequence. Phase θ denotes the actual phase of the three-phase system. If the tracked phase θpll is used for the Park Transformation and it has a small error δθ, i.e. θpll =θ+δθ, the relationship between Udq and δθ is derived in (12).
Since δθ is assumed to be small, sin(δθ)≈δθ. Therefore, qaxis voltage Uq=-U1•sin(δθ)≈-U1•δθ. Based on this conclusion, the equivalent small-signal model of the RCA-PLL can be drawn as in Fig. 5(a), where, the Uq * denotes the q-axis voltage when δθ=0. Therefore, if the system is balanced and do not contain ripple, Uq * =0. Following the discussions in Section II, if the three-phase system is not balanced or contains ripple, Uq * will contain ripple.
As illustrated in Fig. 5(a), the RC is used to track the a.c. part (i.e. ripple part) of Uq * , whereas, the PI controller is used to track the d.c. part (which is always zero) of Uq * . Ideally, at steady-state, Uq com cancels the entire ripple in Uq * , and the d.c. value of Uq err is regulated to zero by the PI controller, such that the phase tracking error δθ=0. Fig. 5(b) shows the equivalent diagram of the system in Fig.  5(a). The system stability is ensured if each of the three parts in Fig. 5(b) is designed to be stable [24].

C. Tuning of the RCA-PLL
In fact, Part 2 in Fig. 5(b) is the closed loop system without RC. Therefore, the first step of the RCA-PLL tuning procedure is to tune the PI controller without considering the RC.
The relationship between proportional and integral gains (Kp, Ki) of the PI controller and natural frequency, damping factor (ωn, ζ) is given by (13), as derived in [22].
Part 1 in Fig. 5(b) is exactly the denominator of the RC equation in (7). By substituting z with e jωTs , the term (1-Qrcz -D ) can be expressed as 1-Qrce -jDωTs . Its minimum value (1-Qrc) is achieved when DωTs=2πi, i=0, 1, 2…, i.e. ω=2πifd. By setting Qrc to one, the system response will be zero for inputs at the fundamental frequency fd and its multiple frequencies.
Sill with reference to Fig. 5(b), from the discussion above regarding Part 2 and Part 1, we can determine that input and output of Part 3 is bounded. For bounded systems, the small gain theorem can be applied to guarantee system stability. Part 3 will be stable if (14) is verified. Hence, the choices of Grc and Qrc should satisfy (14).

-MAF(e jωT s)e j(D-1)ωT s] 1+PI(e jωT s )•G p (e jωT s )
| <1 In this paper, Grc and Qrc are chosen to be 1 and 0.8 respectively, the natural frequency ωn and damping ζ are chosen to be 62.83 rad/s (i.e.10 Hz) and 0.791 respectively. The peak value of the positive sequence in the three-phase system U1 is 311.1 V (i.e. 220 V RMS). Calculating from (13), kp=0.32 and ki=12.7.

D. Zero Error Tracking Proof
According to Fig. 5(a) and equation (7), the error Uq err (z) can be expressed as in (15).
As Qrc=1, D=fs/f̅ pll=1/(Tsf ̅ pll) and, at steady-state, the tracked frequency f̅ pll equals the fundamental frequency fd of the threephase voltage, it can be seen that (16) equals zero when the frequency ω 2π is an integer multiple of fd and it is below the Nyquist frequency. Equation (17) implies that at steady-state, zero error tracking of Uq * can still be achieved when harmonics are present in Uq * .
being Ts the sampling interval, n the grid voltage angle, n the grid angular frequency, an the derivative of the grid angular frequency, yn the computed value of the phase angle. On the basis of dynamic model (19), the prediction-correction filter performs the following two steps: 1) prediction of the state at the subsequent sampling instant: x n =Ax n-1 (20) 2) correction of predicted state on the basis of the prediction phase error e n =θ n -c T x n : x n =x n +ge n (21) Coefficients g1, g2 and g3 of the correction vector g T = [g1 g2 g3] can be selected following the design procedure described in [17].

V. EXPERIMENTAL TESTS RESULTS
An experimental test rig has been built to compare the SRF-PLL, the SSLKF-PLL, and the proposed RCA-PLL. As shown in Fig. 7, a programmable AC source (Chroma) is used to generate the distorted three-phase voltages. It is worth mentioning that, although the three-phase voltages generated by the Chroma are balanced and have no d.c. offsets, due to the inaccuracy of the measurement chain components (sensors, signals conditioning circuits and ADCs), all the tests are affected by a 1.73% unbalance in the three-phase voltage measurements, as well as by a 2.5% d.c. offset in phase A, -0.4% d.c. offset in phase B and 0.2% d.c. offset in phase C. The high performance control platform, ucube [25], is used to implement the PLL solutions, while the experimental results are plotted using Matlab.
A 50Hz, 220V (RMS) three-phase system has been tested under the following five conditions in sequence.
2) Test 2 Second-order harmonic test: On top of the harmonics in the Test 1, the amplitude of phase A in Chroma is set to 10% smaller than the other phases. This means that second harmonics are added to Ud and Uq, respectively.

3) Test 3 First-order harmonic test:
To make the harmonics even more difficult to filter, additional 30 V d.c. offset is added to the phase A, while the other settings in Test 2 remain unchanged. This means that first-order harmonics are added to Ud and Uq, respectively.

4) Test 4 Grid frequency variation test:
Under the same conditions as in Test 3, a ±0.5 Hz variation in the fundamental frequency is applied to the three phase voltages.

5) Test 5 Phase jump test:
Under the same conditions as in Test 3, and fundamental frequency equals to 50Hz, a phase jump of -50° is applied in the three-phase voltages.
The waveforms of the three-phase voltages under the aforementioned five conditions are summarized in Fig. 8.
During the tests, the natural frequencies of the closed-loop systems for the three PLLs are kept the same at 10 Hz. Since the disturbance/harmonic rejection ability of the SSLKF-PLL can be enhanced by reducing the system dynamics, the results for when the natural frequency equals to 5 Hz also have been presented. In the following, they will be denoted as "SRF-PLL Fig. 6. Block diagram of a SSLKF-PLL. Fig. 7 Experimental rig (10 Hz)", "SSLKF-PLL (10 Hz)", "SSLKF-PLL (5 Hz)" and "RCA-PLL (10 Hz)". Moreover, the real phase of the phase A voltage at steadystate is computed offline by using Fast Fourier Transformation (FFT). The phases identified by the three PLLs are compared with this real phase to verify their effectiveness.
Overall, the frequency and phase tracking performances of the three PLLs are discussed in the following three subsections, while the benefits and the drawbacks of the tested PLLs are summarized in the fourth subsection.

A. Steay-state Performance
The tracked frequency and phase error waveforms under all the five test conditions at steady-state are shown in Fig. 9 and Fig. 10, respectively. Those results are also shown in the frequency-domain in Fig. 11 by applying FFT.
As shown in Fig. 9, the RCA-PLL has the best frequency tracking. Although the frequency tracking errors of the SSLKF-PLL (10 Hz) are already more than 80% reduced compared with the SRF-PLL, and the SSLKF-PLL (5 Hz) is even better (more than 95% error reduction), only the RCA-PLL can remove almost completely the estimation ripple and achieve remarkable frequency tracking of the fundamental frequency. For comparing the phase tracking, it is more convenient to perform a comparison in the frequency-domain; to this aim, from the plots shown in Fig. 11, it can be noticed that only the RCA-PLL can remove all the undesired harmonics from the 1 st order to the 12 th order.
It is also worth pointing out that although the SSLKF-PLL tracks the frequency much better than the SRF-PLL, the phase tracking errors of the latter is conversely lower when their natural frequencies are both equal 10 Hz.
Besides, it is worth emphasising that the PI tuning in the RCA-PLL (10 Hz) is the same as in the SRF-PLL (10 Hz). Hence, the results prove that by adding RC, the disturbance rejection ability is effectively enhanced without changing the PI.
Overall, the RCA-PLL has the best frequency and phase tracking performances at steady-state. Its disturbance/harmonic rejection ability is the strongest among the three tested PLLs at steady-state. A clear benefit of the RCA-PLL is that its ripple reduction ability does not vary for different frequencies, whereas the SSLKF-PLL attenuates the higher order harmonics more effectively than the lower order harmonics.

B. Dymanic Performance
The initial transients of the tracked frequency and phase error waveforms in Test 3, the transients during the grid frequency variation in Test 4, and the transients due to the phase jump in Test 5 are shown in Fig. 12 and Fig. 13, respectively.
A clear drawback of using the SSLKF-PLL (5 Hz) is that it is dynamically slow. Therefore, when tuning the SSLKF-PLL, the trade-off between the harmonic rejection ability and its dynamics need to be considered. Conversely, the RCA-PLL can reduce the harmonics without sacrificing its dynamic performance. As shown in Fig. 12 and Fig. 13, the RCA-PLL behaves the same as the SRF-PLL at the beginning, when the PLLs are initialized in the Test 3 and when the phase jump occurs in the Test 5. This is because the RC is disabled during such transients. When these transients are about to terminate, the RC in the RCA-PLL takes effects and improves the steadystate performances.
Another type of transient worth mentioning is the grid frequency variation. As shown in Fig. 12 and Fig. 13 for the Test 4, thanks to the Lagrange fractional delay filter used, the RC is adaptive to such variation and it is effective to reject harmonics even during this transient. Fig. 13 illustrates the differential phase obtained subtracting the phase identified by the RCA-PLL from the phases identified by the SRF-PLL/SSLKF-PLL. The resultant three waveforms in Fig. 13 are like the Test 4 results in Fig. 10. This indirectly confirms that the RCA-PLL identifies the phase more accurately. What is more, this paper focuses on the grids within the ENTSO-e standard, however, it is possible to apply the proposed RCA-PLL for larger frequency variation from 47.5 Hz to 51.5 Hz. The frequency and phase tracking performances are similar to the Test 4 results in Fig. 12 and Fig. 13.

C. Computational Effort
The algorithm execution time for the three PLLs is measured within the ucube control platform, obtaining for the SRF-PLL 5 μs and for the RCA-PLL and the SSLKF-PLL around 12 μs. This confirms that the proposed method can be implemented in the most common control platforms. Some commonly used solutions have been adopted in the implementation of the RCA-PLL to reduce computational burden: 1) Reduced computation in the moving average filers: Since only one value of the 400 values in the MAF is replaced in each period, the sum can be easily updated by subtracting the value to be replaced and add the new value.
2) Use a Farrow structure for the fractional delay filter: A Farrow structure [27] is used for the fractional delay filter to make it more computationally effective. The order of the fractional delay filter is chosen to be six, considering the tradeoff between the interpolating accuracy and the computational load.
3) Use of pointers for updating the arraies: In the RC, the tracked frquency fpll and the error in the q axis voltage Uq err are all recorded using arraies. There is no need to shift the entire array each time it updates, the arraies are updated simply by replacing the oldest values.

D. Benefits of the RCA-PLL
The RCA-PLL has fulfilled the design requirements mentioned in Section II, and its benefits can be summarized as below: 1) In order to maximize the disturbance/harmonic rejection capability, RC is chosen for its ability of rejecting all harmonics without pre-knowing which orders of harmonics are contained in grids. Only two parameters (i.e. Grc and Qrc) need to be tuned, and once they are tuned, the RC can learn the ripple component in the Uq err and provide a compensation action Uq com to cancel only the ripple in Uq.
2) For generating the correct compensation action, at least one cycle (i.e. 0.02s for the 50 Hz system) of learning period is required for the RC to take action. This long delay is a drawback of the RC in some applications but does not affect the performance of the proposed PLL since RC is not responsible for the system dynamics. Thus, superior harmonic rejection is achieved at steady-state without interfering with the dynamic actions of the PI controller.
3) The transient detector disables the RC during transients either due to the PLL start-up or due to a phase jump. For other cases, like grid frequency variations, there is no need to disable the RC since it is adaptive to variable frequency. The traditional RC assisted PLL in [22] can only work at fixed frequency, since its delay line must be a fixed integer. However, the RC used in this work can adapt the length D of its delay chain online by making use of the tracked frequency fpll (the average value of fpll is an accurate approximation of the real frequency), and D can be a fractional number due to the Lagrange fractional delay filter used. 4) In total, two MAFs and one 6 th order Lagrange fractional delay filter are used in this implementation. However, the execution time of the RCA-PLL is only 12μs according to discussion in the previous subsection.

VI. CONCLUSION
A novel Repetitive Controller Assisted PLL adaptive to grid frequency variation has been proposed in this paper for the first time. The RCA-PLL has superior disturbance rejection capability. The orders and amplitudes of the target harmonics are not required for its design. The RCA-PLL can self-learn and cancel a wide range of harmonics from as low as the fundamental (i.e. 50 Hz) to the Nyquist frequency. In comparison to others widely used techniques, it can achieve superior frequency and phase tracking at steady-state, without compromising dynamic performances during phase jumps or other transients. Experimental test results have shown that accurate frequency and phase tracking is achieved for all tested conditions not only at steady-state, but also during grid frequency variations. As a further benefit, the computational burden of the RCA-PLL is low. Its execution time is just 12 μs, which is feasible even using most common industrial grade microcontrollers.