Operation principles of quasi Z-source modular multilevel converters

This paper proposes the integration of a quasi Z-source network with a modular multilevel converter (MMC) to provide voltage boost capability. The proposed quasi-Z-source MMC uses two symmetrical networks of inductors and capacitors connected between the two terminals of the DC-input source and the MMC DC-link. The operation principle, a suitable PWM method and a capacitor voltage balance strategy are proposed. The limitations of the proposed circuit are identified and a solution of using bidirectional quasi-Z-source-networks is identified. The simulation results presented in the paper verify the operation and the performance of the proposed topology.


I. INTRODUCTION
The development of medium voltage DC (MVDC) grids has received considerable attention in recent research papers [1,2]. The implementation of MVDC distribution grids as an alternative to AC grids has advantages in terms of grid system efficiency [3], reliability and overall operating costs [2]. As a result of the emergence of MVDC grid, voltage source multilevel inverters (MLIs) are needed to interface the different parts of the grid. MLIs are preferred due to their attractive features compared to two-level voltage source inverters (VSIs) [4]. Among of multilevel topologies, the MMC has gained increasing acceptance in both medium and high voltage applications. The modular multilevel converter (MMC) is a relatively new topology which has been proposed by Marquardt et al in 2002 [5]. It is able to overcome many of the difficulties of other multilevel converter topologies and provides features such as design modularity, voltage and power scalability, failure management capability and better harmonic performance [6]. As well as being considered for high voltage applications such as high voltage DC (HVDC) [7], the MMC is now being considered for MVDC applications as well [8]. In order to maximise the functionality, it can be expected that MVDC grids will be required to supply AC loads with a voltage higher than their corresponding DC voltages. However, similar to conventional voltage source inverters, the MMC has no voltage boost capability so the peak output voltage is limited by the DC link voltage. In order to be able to achieve a MMC based circuit with both voltage buck and boost capabilities, this paper proposes that the impedance network concept [9] to be integrated with the basic MMC topology. Among impedance network topologies, quasi Z-source (qZS) network has attractive advantages, for example drawing a continuous input current and therefore lowering the source current stress as well as having a reduced capacitor voltage rating requirement [10]. Therefore, qZS network can be suitable for various applications such as photovoltaic (PV) system. Despite the various features for qZS and MMC, there is a gap in literature regarding their possible integration. This integration is proposed in this paper, the resulting converter being referred to as the quasi Z-source modular multilevel converter (qZS-MMC). This converter can work in both buck and boost modes. This paper gives a detailed circuit analysis of the proposed qZS-MMC with a focus on the operating principles and converter performance. The equivalent circuit of the qZS-MMC with the implemented sinusoidal pulse width modulation (SPWM) boosting scheme is presented. Then, the MMC capacitor balancing strategy is introduced and the operational limits and potential disadvantages of the proposed topology are found. This paper also suggests some modifications to the proposed topology, that will result in a bidirectional quasi Zsource modular multilevel converter (BqZS-MMC), that will improve the performance of the converter. Finally, the operation and analysis of the proposed converter is validated using simulation results.

II. OPERATION PRINCIPLES OF THE MODULAR MULTILEVEL CONVERTER
The topology of a single-phase three-level modular multilevel converter (MMC) is shown in Fig. 1 ina as shown in Fig. 1, The load and arm currents can be expressed by: where icir is the circulating current which is responsible for equal charging and discharging of all sub-modules capacitors so each of them has equal average DC voltage. This current contains DC and AC components which flows through the two arms and has no influence on the load currents. The circulating current can be expressed by: where Idc is the DC component which is responsible for transferring real active power from the supply to the load. The AC component i2f is a result of the switching process. It is reported that these AC components contain even order harmonics, with the second order one is the most significant one. Therefore, in this research, the MMC circuit can be simply represented by a continuous DC current source Idc, and two AC current sources, one accounting for the fundamental load component ia and other one for the second order harmonic component (i2f) as shown in Fig. 2.

III. THE PROPOSED QZ-SOURCE MMC AND ITS ANALYTICAL MODEL
The simplified representation of the proposed quasi Z-Source modular multilevel converter (qZS-MMC) is shown in Fig. 2. The circuit consists of two identical qZS networks which are inserted between the DC source and the MMC leg. Assuming a split DC-link is typically needed from the DC-source to connect the half bridge inverter to an AC load, then the two networks need to have a midpoint node between the two capacitors Cu1, Cn1 that can be used as a reference point for the output voltage. The operating principle of the qZS network [10] requires the introduction of p/n short circuit at its terminals in order to increase the energy in the qZS network inductors that is later transferred in the qZS network capacitors and finally this extra voltage provides the voltage boosting capability. The qZS network operates in two modes, shootthrough (ST) mode and non-shoot-through (NST) mode during the switching cycle T equals 1/fs where fs is the switching frequency. The steady state analysis of qZS networks in each mode is carried out assuming that: Cu1=Cn1, Cu2=Cn2 and Lu1=Ln1=Lu2=Ln2. In the following analysis, assuming the voltages and the currents have their average value, the capacitor voltages and inductor currents are given by: In this study, the shoot-through intervals are inserted into the circuit during the zero states of the output voltage levels. For simplicity, two switches Su and Sn are included at the two networks end-terminals to provide ST current path to the DClink midpoint, but the ST functionality can be implemented also by the MSs The performance of the two qZS networks in each mode can be analysed as follows: A. Shoot-through mode (ST) This state begins when the one or/and two networks terminals are shorted by turning on Su or/and Sn which forces Du and Dn to become reverse biased and therefore replaced by an open circuit. In this paper, shoot-through intervals are inserted during zero output voltage, so all SMs in MMC side need to be bypassed. In this mode, the stored energy in the qZS-capacitors begins to transfer to inductors. So inductor currents increase and capacitor voltages decrease. The equations for this equivalent circuit can be written according to [10,11] as follows: The network capacitor currents can be obtained as follows:

B. Non-Shoot-through mode (NST)
In this mode, Du and Dn are forward biased, the stored energy of qZS-networks inductors begins to transfer to the load and Cu1, Cu2, Cn1 and Cu2 begin to charge. So, the capacitor voltages increase and inductor currents decrease. Expressions for this equivalent circuit can be written as: The network capacitor currents can be obtained as follows: The qZS networks diode currents relations as a function of their corresponding arm current are given as follow: The converter switching period T can be expressed by T=Tsh+Tnst, where Tsh is the shoot-through interval, and Tnsh is the non-shoot-through interval.
Let dsh and dnst be the ST and NST duty ratios respectively defined by: At steady state, the average value of the inductor voltages over one switching period equals zero. Therefore, the average capacitors voltages (Vc1 and Vc2) are given by: Substituting from (10) into (6), and assuming that vpn, vpo and von are constant and equal to their average value Vpn, Vpo and Von during NST intervals, the dc-link voltage during NST mode and the peak value of the fundamental output phase voltage (Vm) are derived: where M is the converter modulation index and B is the voltage boost factor which is given by The possible operation range of dsh is from zero to 0.5. Therefore, B varies from 1.0 to infinity. When setting dsh=0, the converter works in buck mode. According to (8), it is noted that the diodes are forward bias during non-shoot-through intervals when upper or lower arms currents are smaller than double of average inductor current. Otherwise, the diodes will be reverse biased. The boundary where the diodes state change naturally from forward to reverse bias and the implication in the operation of the circuit and its performance are investigated thoroughly in section V.

IV. MODULATION SCHEME AND MMC CAPACITORS VOLTAGE BALANCING
A. Modulation scheme To synthesize a three-level voltage waveform at the converter AC-side, phase opposition disposition SPWM (POD-SPWM) is used in this study to control the qZS-MMC. For the three-level MMC, two triangular carriers (c1 and c2) with the same frequency and amplitude are required as indicated in Fig.  3. Each carrier is responsible for producing the gating signals of two complementary cells (one from upper and one from lower). A reference modulating waveform is compared against the two carriers to define which leg-switches are conducting. If the reference waveform is higher (lower) than the two carriers, positive (negative) voltage levels at load terminals are produced respectively, otherwise, zero voltage level is generated. A zero voltage level can be produced by any of the four switching states which are named redundant states that can be selected to guarantee voltage balancing among SMs capacitors [10]. Shoot-through switches Su and Sn are controlled by employing another modulating signal Vsh which has a positive DC value equal to peak value of the reference modulating waveform and intersects with the upper triangular carrier C2 as shown in Fig. 3. The ST intervals occur only when carrier signal C2 is greater than Vsh which means that all sub-modules are bypassed. The relation between modulation index M and dsh is given by: As mentioned earlier, dsh is in the range between 0 and 0.5, therefore, M operation range is limited from 0.5 to 1.

B. Capacitor voltage balance
The MMC requires a voltage balancing strategy to balance and keep the sub-modules capacitor voltages at their desired average values. The implementation of balancing strategies depends on the presence of the redundant states. For the threelevel MMC, the redundant states are four which only synthesize the zero voltage level. The redundant switching state with the strongest effect in facilitating voltage balancing is always selected. The MMC arm capacitors balancing can be achieved by different strategies [11]. The most widely used balancing strategy is based on the sorting method [6] which is summarized in four steps as follows: 1) Measure and sort the upper and lower capacitor voltages; 2) From modulation scheme, determine the number of inserted cells (np and nn) from upper and lower arms respectively; 3) If the upper (lower) arm current is positive, choosing the np (nn) cells with lower voltage to be inserted. Therefore, the corresponding cell capacitor is charged and its voltage increases; 4) If the upper (lower) arm current is negative, choosing the np (nn) cell with higher voltage to be inserted. Therefore, the corresponding cell capacitor is charged and its voltage decreases.

V. OPERATING MARGINS OF QZS-MMC
In this study conducted, the values of inductances and capacitances are assumed to be sufficiently large so that the inductor currents and capacitor voltages have negligible ripple. As stated previously, during ST mode, the diodes will always become reverse biased. However, during NST mode, the two diodes Du and Dn are forward biased if the following conditions are met, otherwise the diodes will be reverse bias.
According to (14), if ipa (ina) becomes higher than twice the inductor current 2IL, Du (Dn) will become reverse biased and ipa (ina) will be equal iLu1+iLu2 (iLn1+iLn2). As a result, the upper (lower) dc-link voltage Vpo (Von) given by (11)  where cosϴ is load power factor (PF). The average value of capacitors' currents during switching period T equals zero. So by using (5) and (7), Idc can be expressed by: Substituting from (13), (16) and (17) into (15), the peak value of two arms currents is given by: By comparing (14) with (18), the condition for the diodes to be forward biased during NST intervals is given by: From (13) and (19), the M value is restricted by: (20) shows that the allowable modulation index range depends on the PF. At unity PF, M operation range is 0.5<M<0.75 and this range reduces gradually by having a more inductive load. The drawbacks caused by this configuration are: i) dropping in overall DC-link voltage during non-shootthrough mode especially at M>0.75 at unity PF. ii) overcharging of all converter capacitors which may lead to converter elements damage. iii) working only in boost mode, not applicable in buck mode. iv) applicable only with unity and inductive PF. The reasons for these limitations and drawbacks in qZS-MMC are the two uncontrolled diodes (Du and Dn) that have their states dependent on the circuit operating conditions such as, modulation index and load PF. These two diodes play a dominant role in the DC voltage boosting and cannot be removed. The solution to address these drawbacks to the qZS-MMC operation is to insert two active switches (IGBT) in antiparallel with diodes as shown in Fig. 4. This novel resulting topology is referred as a bidirectional quasi Z-source MMC (BqZS-MMC) and is investigated in the following section.

VI. NOVEL BIDIRECTIONAL QUASI Z-SOURCE MMC (BQZS-MMC)
The topology of BqZS-MMC is shown in Fig. 4. The idea of adding two additional controllable switches (Tn and Tu) is not only to expand the range of M and PF of qZS-MMC during the inversion process, but also to add the possibility of power returning back to the supply during regenerative operation. In this research, the BqZS-MMC is investigated during inversion mode (power flows from DC source to AC load) only. The additional switches can be controlled simultaneously by a gate signal which is a complement to the shoot-through gate signal illustrated in Fig. 3. In order to simplify the analysis of the second proposed topology, the BqZS-MMC circuit can be divided into two parts (upper and lower parts) as shown in Fig.  4. The upper (lower) part circuit may be analysed in two different regions (U-1 and U-2) as shown in Fig. 5 which is depending on the instantaneous values of the upper (lower) arm current and average value of the inductor currents (IL) as detailed earlier in Section V.
In each region, there are two modes, ST and NST modes. Once more, the ST mode in the two regions is identical to the previous analysis in section III. The difference will appear in the NST mode, where the capacitors charging and discharging will depend on which semiconductor devices (Du, Tu, Dn and Tn) are conducting. However, qZS network inductors are discharging as their stored energy moved into the qZS network capacitors and the load regardless of the operation regions. The following description is carried out on the upper-part and consequently, the lower-part circuit will be similar. The waveforms of the upper arm current and upper-part capacitor voltages over output voltage cycle are shown in Fig. 5. The NST mode in the two operation regions of upper part circuit are described as follow: a) Upper-region U-1 when 2IL<ipa (t): This region appears when the upper arm current is higher than 2IL, as shown in Fig. 5. Therefore, according to (14), Du will become reverse biased. So, Tu must be turned on to avoid any drop in dc link voltage caused by discontinuous conduction, as discussed earlier. Upper capacitors (Cuj), where subscript j equals 1 or 2, are discharged by a rate which can be expressed by: b) Upper-region U-2 when 2IL>ipa (t): Du is forward biased because ipa is smaller than 2IL. If ipa waveform decreases below 2IL but remain higher than IL, the upper-part capacitors are discharged by rate which given by (21). Then, once ipa equals IL value at point "x" as shown in Fig Fig. 2 and Fig. 4. The parameters used in the simulation models are given in Table 1. The simulation study has been carried out using an inductive load with PF=0.95 and considering that all system components and switches are ideal. The simulation results corresponding to the qZS-MMC and BqZS-MMC at different values of modulation index for both buck and boost modes are shown in Fig. 6 to Fig. 8.
Firstly, the modulation index M is set to 0.7 and consequently the shoot through duty ratio dsh is set at 0.3 according to (13). The two topologies will produce the same response. The reason is that both arm currents are always lower than twice the inductor current, as discussed earlier. According to (20), there is not any current will path through the two switches (Tu, Tn) at modulation index lower than 0.74. Fig. 6a illustrates the upper and lower arm currents and their DC link voltages. It is clear that there is no drop in the MMC DC-link voltage at M=0.7. Fig. 6b shows the arms capacitor voltages which are charged at their expected average value of 248V which is equal to the upper (lower) DC link voltage given by (11). In addition, the qZS-network capacitors' voltages are shown in Fig. 6b. These capacitors are charged at their expected average values Vc1 and Vc2 which equals 174V and 74V respectively. Load voltage and current and their harmonic spectrums are shown in Fig. 6c.
The second test is carried out at M=0.9 and dsh=0.1. As shown in Fig. 7a, it is clear that when the waveforms of both arm currents are higher than twice the inductor current (2IL), the upper or lower DC-link voltages will drop. When the two additional switches are connected in antiparallel to the qZSnetwork diodes, the DC-link voltage never drops, as expected in BqZS-MMC topology and this is shown in Fig. 8a. Fig. 7b and Fig. 8b show the voltages of the two arms and the qZSnetwork capacitors of the two converters, the qZS-MMC and the BqZS-MMC respectively. The capacitors in qZS-MMC are overcharged where according to (10), the expected average values of network capacitor voltages Vc1 and Vc2 are 112.5V and 12.5V respectively. The average resultant network capacitors voltages are 122V and 22V as shown in Fig. 7b. In addition, the expected average value of the arms capacitors' voltages is at the peak value of half of the DC-link voltage which equals 125V as predicted by (11). The average value of the arm capacitor voltages is 135V as shown in Fig. 7b. Fig. 8 shows the same set of results but for the BqZS-MMC. It can be seen that all capacitor voltages are at their expected values as  Fig. 7c and Fig. 8c respectively. The two topologies achieve approximately equal amplitude of fundamental voltage (173V at M=0.7). By setting M to one at a source voltage of 200V, the obtained peak value of the fundamental voltage using the proposed converter will be 247V at dsh=0.3, which is higher than 100V (one half of the source voltage) that could be obtained from a traditional MMC without qZS-network. As is clear from Fig. 7c and Fig. 8c, the BqZS-MMC has lower low order harmonics (3 rd , 5 th and 7 th ) and also a slightly lower total harmonic distortion (THD) compared to qZS-MMC. It can be concluded that the simulation results shown in Figs. 6 to 8 are consistent with the theoretical analysis presented in this paper and that the proposed BqZS-MMC performs better than qZS-MMC with a wide range of M, e.g. for a PF=0.95 that has been employed in this study, the maximum value for M is 0.74 for qZS-MMC while BqZS-MMC can operate at higher values.

VIII. CONCLUSION
This paper proposed a novel bidirectional quasi Z-source modular multilevel converter topology that is able to achieve buck and boost voltage capabilities. This converter combines the advantages of both qZS circuit and MMC. An analytical model of the converter has been derived that revealed the limitations of the converter. The models of the proposed configurations were verified by simulation at different modulation indexes in boost mode. The simulation results showed that BqZS-MMC overcomes the weaknesses related to the qZS-MMC such as, eliminating DC-link voltage drops, better output voltage and current harmonic spectrums and avoiding overcharging the converter capacitors.