10-kV SiC MOSFET Power Module With Reduced Common-Mode Noise and Electric Field

The advancement of silicon carbide (SiC) power devices with voltage ratings exceeding 10 kV is expected to revolutionize medium- and high-voltage systems. However, present power module packages are limiting the performance of these unique switches. The objective of this research is to push the boundaries of high-density, high-speed, 10-kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10-kV devices. The high-speed switching and high voltage rating of these devices causes significant EMI and high electric fields. Existing power module packages are unable to address these challenges, resulting in detrimental EMI and partial discharge that limit the converter operation. This article presents the design and testing of a 10-kV SiC mosfet power module that switches at a record 250 V/ns without compromising the signal and ground integrity due to an integrated screen reduces the common-mode current by ten times. This screen connection simultaneously increases the partial discharge inception voltage by more than 50%. With the integrated cooling system, the power module prototype achieves a power density of 4 W/mm3.

Due to the vast possibilities for ≥10-kV SiC devices, many resources have been devoted to their development. To date, the majority of the reports on these devices have been focused on the characterization [6], [11], [19], [22], [23], gate driver design [24]- [27], and converter evaluation [11], [23], [28]. However, the packaging of the semiconductor dies has a significant impact on the performance, and is currently hindering their switching speed, voltage rating, current rating, and operating temperature. It is nontrivial to design a suitable package for 10-kV SiC MOSFETs. In addition to the well-known electromagnetic and thermal challenges associated with packaging WBG devices, the high voltage rating creates impeding electrostatic and electromagnetic interference (EMI) issues, which must be addressed to utilize the full capabilities of these devices.
The first-generation 10-kV SiC MOSFETs were assembled into a power module using a modified 6.5-kV silicon nsulated gate bipolar transistor (IGBT) package [29]. Upon analysis and testing of the power module, it was found that the parasitic inductances and capacitances were large and unbalanced [30], limiting the dynamic performance and causing significant EMI. An improved package for third-generation 10-kV SiC MOSFETs was presented in [31]. This package has lower and more symmetrical parasitic inductances [31], though the improvement in the EMI is unknown.
EMI arises from the voltage and current transitions occurring during operation of the switching cell, and can be conducted through the electrical connections, or radiated into the surrounding space. Typically, filters are added to reduce the EMI; however, these increase the cost, size, and complexity of the power conversion system. Adding large external filters diminishes the power density and simplicity benefits gained by using 10-kV SiC MOSFETs. In particular, conducted common-mode (CM) noise is a major issue with high-speed devices. CM noise is caused by the high-dv/dt switching of the semiconductor devices, which causes current to flow through the parasitic capacitances. These capacitances exist in the power module and auxiliary circuitry, such as the gate driver isolation. The latter has been addressed in other works by reducing the isolation capacitance of the gate driver power supply [24]- [27].
To address the issue of current flowing through the parasitic capacitances within the package, [32] proposed a method for diverting the current back to the dc bus by using two stacked direct-bonded-copper (DBC) substrates, where the intermediate metal layer is connected to the positive or negative dc bus. The amount of current that is diverted will depend on the high-frequency impedance of the connection back to the dc bus. Accordingly, the implementation of this screen is critical. In [32], wire bonds are used for the interconnections, and lugs are used for the terminals. These connection methods may have large parasitic inductances, which could reduce the effectiveness of the screen.
In [33], a similar screen is proposed. The 1.2-kV SiC MOSFET power module in [33] uses a multilayer DBC substrate, and dc-link capacitors located close to the dies. Vias in the multilayer substrate create a low-inductance connection between the middle metal layer and the negative dc bus [33]. The module has a 14 dB reduction compared to the reference module [33], [34]. While this module has several advantageous features, there are some areas for improvement. First, by connecting the middle metal to the negative dc bus, as in [32], the top ceramic is providing all the voltage isolation, and thus the second ceramic is not being fully utilized. Second, by placing the capacitors on the same plane as the MOSFETs, the footprint of the module is increased. Third, the module parasitics are not well balanced, which has been shown to cause greater high-frequency noise compared to balanced designs [35].
The high-voltage rating of the 10-kV SiC MOSFETs poses a challenge for the electrostatic performance. If the electric field exceeds the breakdown field strength of the insulation materials, such as the encapsulation or insulating substrate, then partial discharge (PD) can occur. Repetitive PD events can ultimately result in insulation failure, such as cracking of the ceramic substrate, as shown in [36], which could cause a short circuit between the dc bus and ground. Furthermore, the PD inception voltage (PDIV) has been shown to decrease with increased dv/dt and switching frequency [37]. Due to the high-speed switching capabilities of these 10-kV SiC MOSFETs, measures must be taken to reduce the electric field concentration within the power module to ensure sufficient PDIV and breakdown voltage.
In this work, a high-voltage power module package was designed, prototyped, and tested using 10-kV SiC MOSFETs. With the proposed package, the 10-kV SiC MOSFETs are able to switch at record speeds with minimal ringing and voltage overshoot. This fast switching results in significantly reduced switching losses compared to medium-voltage silicon transistors, and allows the switching frequency of medium-and high-voltage converters to be increased by orders of magnitude, which drastically reduces the size of passive components, thereby increasing the system power density. To mitigate the conducted EMI that could result from this high dv/dt, this work proposes to fully integrate a low-inductance screen into the package that limits the amount of CM current that flows out of the power module.
In this implementation, the screen layer is connected to the dc bus midpoint, which evenly distributes the electric field in the ceramic substrates and reduces the peak electric field at the critical triple points. The dc bus midpoint connection is made through embedded series capacitors that are arranged above each MOSFET switch pair. Thus, the proposed implementation will mitigate the CM current, while also improving the voltage isolation, increasing the PDIV of the power module, and maintaining a small footprint for high power density.
In this article, the EMI issues encountered during testing of the first-generation 10-kV SiC power modules from [29] will be presented, followed by a description of the proposed power module for 10-kV SiC MOSFETs. The analysis, implementation, and preliminary testing of the integrated CM screen will then be discussed. Methods for reducing the electric field concentration within the power module will be reviewed, and the proposed technique will be analyzed. Finally, the experimental switching tests that demonstrate the high-speed transients and low CM current of the proposed package will be presented. Partial discharge tests validating the improved voltage capability provided by the CM screen will also be shown.

II. EMI LIMITATIONS FOR HIGH-VOLTAGE SIC POWER MODULES
The development of 10-kV SiC MOSFETs [38] and 10-kV SiC junction barrier Schottky (JBS) diodes [40] gave rise to the first 10-kV SiC power module [29]. The half-bridge modules comprise 12 parallel 10-kV, 10-A SiC DMOSFETs, and six parallel 10-kV, 10-A SiC JBS diodes, per switch position, yielding a current rating of 120 A [29]. These 10-kV SiC modules demonstrated higher efficiency and switching frequency potential than 6.5-kV silicon IGBT modules [8], and were critical components in the development of a high-density 1 MVA solid-state power substation, which employed soft switching techniques and was capable of switching up to 20 kHz [40]. These modules were also used to demonstrate the first medium-voltage impedance measurement unit capable of characterizing in-situ source and load impedances of dc and ac networks up to 4160 V ac, 6000 V dc, 300 A, and 2.2 MVA [41]. Unfortunately, the full voltage and power levels could not be achieved due to significant, unresolvable EMI. Upon further evaluation, it was found that substantial current was flowing through the system ground. The contaminated ground was causing the controller to malfunction, thereby limiting the operating conditions. During voltage transients, parasitic capacitances can become a path for CM current to flow. Within the power module, parasitic capacitances exist across the ceramic substrate that isolates the semiconductor devices from the cooling system. Since the cooling system is generally grounded for safety, under highspeed voltage transients, this parasitic capacitance becomes a path for CM current to flow through the system ground [35]. Therefore, this capacitance should be minimized, especially for fast-switching devices.
From ANSYS Q3D simulations, the parasitic capacitance between the output node of the half-bridge and the module baseplate is approximately 300 pF. Discrete switching tests were conducted on these power modules to characterize the dynamic performance [42]. At 4.7 kV and 100 A, the power modules had a maximum dv/dt of 22 V/ns [42]. This measured dv/dt and simulated parasitic capacitance give a calculated peak current of nearly 7 A. It should be noted that the 22 V/ns switching speed was achieved with internal and external gate resistances slowing down the devices. If these resistances were reduced or eliminated, then the switching speed would increase, which would raise the efficiency, but worsen the CM current. Therefore, this capacitance is limiting the operation of the 10-kV SiC MOSFETs. The package proposed in this work reduces this EMI without sacrificing the efficiency by minimizing the parasitic capacitance, and integrating a screen that contains the generated CM current within the power module. Fig. 1 shows the designed half-bridge power module, which has three 10 kV, 350-mΩ SiC MOSFET dies in parallel per switch position. No external anti-parallel diodes are used. The module has a planar, sandwich structure, using metal posts and directbonded-aluminum (DBA) substrates as the die interconnection instead of wire bonds. Similar structures were proposed in [43] and [44] for lower voltage silicon IGBTs. This type of structure allows for increased power density, and reduces the parasitic inductances and capacitances in the module, thereby improving the dynamic performance. Furthermore, by eliminating the wire bonds, the module will be able to withstand higher energy faults, as shown in [45]. This structure also allows decoupling capacitors to be embedded within the module to further improve the dynamic performance without increasing the module footprint.

III. MODULE OVERVIEW
In total, four substrates are used in the power module: two beneath the dies (DBA1 and DBA2) and two on top (DBA3 and DBA4). DBA1 and DBA2 are used to reduce the CM current flowing through the system ground and to decrease the peak electric field strength within the power module. With . The low-current module was fabricated to test the prototyping procedures, and was used for initial testing. The testing of these module prototypes will be presented in Section VI.

A. Impedance Analysis
In this section, the CM path impedances will be analyzed. Fig. 3 shows a schematic of the power module with the key impedances that will be considered. For the generated CM current to be diverted from the ground to the screen, the impedance of the screen path must be much lower than that of the ground path, especially at high frequency. The condition required for the screen to effectively divert the CM current from the ground path to the dc bus may be summarized as follows: where Z screen and Z gnd are the impedances of the screen and ground paths, respectively. Considering the parasitic elements shown in Fig. 3, these impedances can be defined as follows: where L screen and L gnd are the parasitic inductances in the screen and ground paths, respectively. R screen and R gnd are the parasitic resistances in the screen and ground paths, respectively. C D is the decoupling capacitance and C P 2 is the parasitic capacitance of the bottom substrate, which is connected to ground [see Fig. 1(d)]. As shown by (2), to minimize Z screen , L screen should be as small as possible, while C D should be large. From (3), it can be seen that a smaller C P 2 results in a greater Z gnd . Substituting (2) and (3) into (1) gives the following: From (4), it can be seen that the effectiveness of the screen is dependent on the parasitic elements, which are determined by the implementation. To effectively reduce the CM current, the power module should be compact such that C P 2 and L screen are small, yet capable of accommodating sufficient decoupling capacitance C D . The L gnd and R gnd will vary depending on the system integration, and are therefore out of the control of the power module designer. Accordingly, this work focuses on minimizing C P 2 and L screen , and maximizing C D . A more general theoretical analysis of CM impedances is presented in [49].

B. Preliminary Testing
Prior to constructing the 10-kV SiC MOSFET power modules, it was desirable to understand the effects of the proposed screen on the CM noise. Accordingly, a half-bridge module with 1.2-kV, 80-mΩ SiC MOSFETs (C2M0080120D) was built and tested in a boost converter. For the test, the module substrate was directly mounted onto a copper ground plane. No cooling system was added between the substrate and the ground plane to improve the measurement results. Due to the absence of a cooling system, the tests were conducted at low power (360 W). The output voltage was 60 V, and the switching frequency was 50 kHz.
For the prototyped 1.2-kV SiC modules, the parasitic capacitance from the output node to the middle metal layer, C P 1 , was 20 pF, and the parasitic capacitance from the middle metal layer to the ground, C P 2 , was 150 pF. These values were measured on the prototype using an impedance analyzer, and were verified by calculation and Q3D simulation. C P 2 is larger than C P 1 because the middle and bottom metal layers cover the entire substrate area, whereas the output terminal makes up a small portion of the footprint.
For the tests, a high-frequency current transformer (HFCT) was used to measure the current of the line impedance stabilization network (LISN). The output of the HFCT was connected to an EMC analyzer. The measured current for five cases is shown in Fig. 4. The first case has a single substrate and no decoupling capacitors. The second case has two stacked substrates and no decoupling capacitors. The third case has two stacked substrates and two 680-pF decoupling capacitors in parallel and two in series, but the middle metal layer of the substrate stack is left floating. The fourth case is similar to the third, but has two series 10 nF capacitors. The fifth case connects the middle metal layer of the substrate stack to the midpoint of the series decoupling capacitors.
When two substrates are stacked together (case 2), the noise decreases by just a few decibels compared to case 1 with a single substrate. This indicates that the reduction in the parasitic capacitance offered by the second substrate is not sufficient to lower the CM noise. The addition of 680-pF decoupling capacitors in case 3, on the other hand, reduces the high-frequency noise by more than 10 dB compared to case 1 with a single substrate. The decoupling capacitors also cause the resonant frequency to decrease. When the decoupling capacitance is increased to 10 nF (case 4), then the resonant frequency further decreases, and the high-frequency noise is reduced by a few more decibels. This is in agreement with (2), which shows that increasing the decoupling capacitance reduces the high-frequency impedance of the screen path. When the middle metal of the substrate stack is connected to the midpoint of the two series 10-nF capacitors (case 5), then the high-frequency noise decreases by more than 15 dB over a larger frequency range. This is because there is now a low-impedance, high-frequency path for the generated CM current to flow. This preliminary testing demonstrates the potential of the screen to reduce the CM noise.
The gate-source and drain-source voltages and drain current of the 1.2-kV SiC MOSFET were also monitored during the testing. By adding decoupling capacitors, the ringing frequency in the drain-source voltage reduced, and the di/dt increased, resulting in greater current overshoot and higher-amplitude ringing. This ringing and overshoot can be reduced by decreasing the power-loop inductance, which was not optimized in this module prototype. Connecting the middle metal layer to the decoupling capacitor midpoint did not cause noticeable changes in the MOSFET voltage and current waveforms. Therefore, if the parasitic inductances and decoupling capacitors are carefully designed, the proposed CM screen will have minimal impact on the MOSFET losses.

C. Implementation
To achieve a low-impedance implementation for the CM screen in the 10-kV power module, it is proposed to embed capacitors, and to use vias within the insulating ceramic substrates to make the connection between the middle metal layer and the capacitor potentials. In [49], the capacitors are placed above the semiconductor devices, creating a vertical high-frequency power loop that does not increase the module footprint, as it takes advantage of the third dimension. In this work, this vertical-capacitor-loop concept was adopted with some modifications. Each 10-kV SiC MOSFET switch pair has its own set of decoupling capacitors located above it [see Fig. 1(c)], resulting in a symmetric power loop inductance of just 4.4 nH for each. In this embodiment, two capacitors are placed in series, and the midpoint, which is at half of the dc bus voltage, is connected to the middle metal of the substrate stack. By connecting the screen to the decoupling capacitors within the power module, the influence of the parasitic impedances external to the package are diminished thereby improving the effectiveness of the screen.
According to ANSYS Q3D simulations, this connection method has less than 2 nH parasitic inductance, allowing for a high proportion of the CM current to be diverted to the dc bus and contained within the power module. Additionally, the S1D2 pad area was designed as small as possible to minimize C P 1 . For the proposed high-current 10-kV power module shown in Figs. 1 and 2(b), C P 1 is 46 pF, and C P 2 is 160 pF, according to ANSYS Q3D simulations. For the decoupling capacitors (C D ), a surface-mount 680-pF C0G 5-kV multilayer ceramic capacitor was selected. As shown in Fig. 1(c), there are three capacitors in parallel-one above each MOSFET switch pair-giving an equivalent capacitance of 2.04 nF.

V. ELECTRIC FIELD REDUCTION
To address the enhanced electric field associated with a highvoltage, high-density package, the ceramic substrate must be thoughtfully designed and evaluated. In power modules, the electric field concentrates at the intersection of the ceramic, metal, and encapsulation [51]- [54]. This is known as the triple point. If this electric field exceeds the breakdown field strength of the insulation materials, such as the ceramic or encapsulation, then PD can occur. Repetitive PD events can ultimately result in insulation failure, such as cracking of the ceramic substrate as shown in [36], thus destroying the power module.
In the literature, it has been shown that the PDIV for standard 1-mm thick aluminum nitride (AlN) DBC substrates is less than 10-kV rms [36], and can be as low as 5-kV rms [55]. This does not provide sufficient margin for 10-kV SiC MOSFETs. Accordingly, methods for reducing the peak electric field within the power module need to be explored. There have been several proposed solutions to reduce the electric field strength at the triple point, including increasing the ceramic thickness [36]; varying the metal pad size [36], pad corner curvature [36], offset between the top and bottom pads [36], and metal-ceramic interface geometry [56]- [58]; and stacking multiple substrates [55]. None of these previously proposed solutions were implemented and tested in an actual power module, and several of them may complicate the module manufacturing. The method proposed in this work, is an adaptation of the latter method. It effectively increases the PDIV, and is simple to implement.
In [55], it was shown that stacking DBC substrates reduces the electric field strength within the bulk ceramic and at the critical triple points. The PD tests revealed that the PDIV could be increased by 94% by stacking two 0.32-mm Al 2 O 3 substrates compared to having a single 0.63-mm substrate [55]. However, the practical implementation of this method was not explored. In a power module, the top and bottom metal layers are not symmetrical; the top metal is patterned to create the circuit (e.g., half bridge), and the various traces are at different potentials during the module operation. As a result, it is not clear what potential should be applied to the middle metal layer to achieve a meaningful reduction in the electric field strength. This key factor in the realization of this method is explored in this work. Fig. 5 shows the simulated two-dimensional electric field distribution for the case when the top metal is patterned and has two different potentials. One of the potentials represents the drain of the high-side switch, and the other represents the drain of the low-side switch. The former is consistently at the positive dc bus potential while the latter switches between the positive and negative dc bus potentials. The worst-case scenario is when the low-side switch is conducting and its drain is at the negative dc bus potential. This worst-case was simulated. The positive dc bus is set to 10 kV, and the negative is set to 0 V. The bottom-most metal is at the same potential as the cooling system, which is grounded (0 V). Fig. 5(a) shows the simulated electric field plot for a single DBA substrate. It can be seen that the electric field distribution is non-uniform within the bulk of the ceramic, and that the peak electric field occurs at the triple points. The peak electric field exceeds 20 kV/mm, which is the typical breakdown field strength for ceramic substrates. Fig. 5(b) shows the simulated electric field plot for two stacked DBA substrates with the middle metal layer connected to the negative dc bus (0 V), as proposed in [32] and [33] Comparing Fig. 5(a) and (b), it can be seen that connecting the middle metal to the negative dc bus does not reduce the peak electric field at the triple point, nor does it improve the distribution within the bulk ceramic, compared to the single substrate case. This is because the bottom substrate has 0 V across it, while the top substrate has 10 kV. In this implementation, the bottom substrate is not helping to support the voltage, and is therefore not being fully utilized.
If the middle metal is connected to the positive dc bus, as proposed in [32], then the triple points at which the peak electric field occur will change, and the electric field distribution within the bulk ceramic will shift. This is shown in Fig. 5(c). Although the distribution and critical triple points have changed, the peak electric field, and therefore the PDIV, are similar to the case with a single substrate. This is because both the top and bottom substrates have 10 kV across them.
If instead the middle metal is connected to half of the applied voltage, then both the top and bottom substrates have a potential of 5 kV across them. The simulated electric field distribution for this case is shown in Fig. 5(d). The simulated peak electric field is reduced by 58% compared to the single-substrate case [see Fig. 5(a)], and the electric field in the bulk ceramic is uniformly distributed in the two substrates. Therefore, in this work, the The connection of the middle metal layer to half of the bus potential can be realized with the embedded decoupling capacitors. Each set of decoupling capacitors shown in Fig. 1(c) consists of two, 5-kV ceramic capacitors placed in series. From Fig. 1(d), it can be seen that the midpoint of the capacitors is connected to the middle metal layer of the bottom DBA stack through vias and metal posts. This connection allows the middle metal layer to be connected to half of the bus voltage, thus reducing the peak electric field in the power module.

A. Switching Testing
To evaluate the switching performance of the proposed 10-kV power module, double-pulse tests (DPT) were performed on the low-current prototype shown in Fig. 2(a). The DPT schematic and setup are shown in Fig. 6. The gate driver used for the DPTs was adapted from the one presented in [59]. The low-side 10-kV SiC MOSFET was driven from +20 V in the ON-state to −5 V in the OFF-state. The body diode of the high-side 10-kV SiC MOSFET was used as the free-wheeling diode. The gate driver PCB is mounted on top of the power module to achieve small gate-loop inductance between the driver and the module.
The gate-source and drain-source voltages of the low-side SiC MOSFET were monitored using a 300-V passive probe with a bandwidth of 1 GHz, and a 20-kV passive probe with a bandwidth of 75 MHz, respectively. As shown in Fig. 6(c), these probes are placed directly above the MOSFET terminals to minimize the parasitic inductance in the measurement loop. Due to the embedded decoupling capacitors, the drain current of the SiC MOSFETS could not be measured. A 15-kV power supply was used to charge the external decoupling capacitors. Each capacitor is 0.82 μF and rated at 3.3 kV (MP80CV824K [60]). Six total capacitors were used-two in series and three in parallel for a total capacitance of 1.2 μF and voltage rating of 6.6 kV. Three capacitors were put in parallel to increase the capacitance and to reduce the inductance; each capacitor has an equivalent series inductance of 30 nH [60]. Fig. 7 shows the gate-source and drain-source voltage waveforms for the turn-ON and turn-OFF transients for the DPTs performed on the module shown in Fig. 2(a). The switching tests were performed up to 5 kV and 20 A with turn-ON and turn-OFF gate resistances of 0.33 and 0.17 Ω, respectively. Table I lists the measured overshoot, undershoot, rise and fall times, and switching rates from the DPTs. During the turn-ON transient, the fall time of the drain-source voltage is 16 ns, giving a dv/dt of 250 V/ns. At turn-OFF, the voltage rise time is 50 ns, which is a dv/dt of 80 V/ns. The voltage rise time is longer because it is controlled by the output capacitance and load current. Negligible voltage overshoot and ringing were measured, indicating low power-and gate-loop inductances. This is due to the low-inductance module design, as well as careful layout and connection of the gate driver, bus bar, external decoupling capacitors, and measurement probes.
To the author's knowledge, these are the fastest switching speeds reported for similarly rated SiC MOSFETs and IGBTs. In fact, this is more than two times faster than those reported in [23], [31], [61], and [62]. In [31], switching results for a module populated with a single die had turn-ON and turn-OFF transition times of approximately 80 and 120 ns, respectively, giving switching speeds of 88 and 58 V/ns at a bus voltage of 7 kV, drain current of 15 A, and gate resistance of 21 Ω. The switching waveforms also showed a moderate voltage overshoot of approximately 300 V (4.3%) [31].
For a discrete 4-kV silicon IGBT, the datasheet reports voltage rise and fall times of 146 and 514 ns at 1.25 kV, 30 A, and 2 Ω external gate resistance [63]. These switching times result in dv/dt values of 8.6 and 2.4 V/ns for the rise and fall, respectively, which are 10 and 100 times slower than the switching speeds achieved in this work. Accordingly, the proposed power module can enable faster switching, higher voltage power converters while maintaining high efficiency.

B. Common-Mode Screen Testing
To evaluate the effectiveness of the integrated CM current screen on the 10-kV power module, switching tests were performed. As mentioned earlier, the CM current increases as the dv/dt and parasitic capacitances increase. To improve the signal-to-noise ratio of the CM current measurement, the dv/dt was reduced. This was achieved by lowering the dc bus voltage to 2 kV. To ensure sufficient CM current could be measured, the larger power module with three 10-kV SiC MOSFET dies in parallel per switch position was used [see Fig. 2(b)] [64]. The C P 1 and C P 2 of this 10-kV prototype are 47 and 162 pF, respectively. Fig. 8(a) shows the schematic of the tests when the CM screen is not connected (the middle metal layer of the bottom substrate stack is floating). Fig. 8(b) shows the schematic of the tests when the CM screen is connected to the capacitor midpoint. An inductor with high-voltage wire for the winding was connected across the high-side switch of the half-bridge module. The body diode of the high-side SiC MOSFET was used to freewheel the current in the inductor when the low-side switch was OFF.
To validate the performance of the CM screen, the current through the ground path, I gnd , was measured, as shown in Fig. 8, using an RF current transformer with a bandwidth of 200 MHz. For these tests, the middle metal layer was connected to the midpoint of the two series 680-pF decoupling capacitors. Three capacitors were placed in parallel. Fig. 8(c) shows the turn-OFF drain-source voltage and ground current waveforms with and without the screen at 2 kV and 20 A with no external gate resistance. The voltage rise time at turn OFF is 66 ns, which gives a dv/dt of 24 V/ns. This dv/dt is lower than the previous switching tests because of the lower bus voltage and larger device capacitance due to the three MOSFET dies in parallel. The measured peak current through the ground path without the proposed screen is 2 A. This peak current will increase as the dc bus voltage, and therefore the dv/dt, increases. With the CM screen connected, the measured peak current through the ground path is reduced to 0.2 A. This is an order of magnitude reduction.

C. Partial Discharge Testing
PD tests were conducted to validate the electrostatic simulation results. The PD tests were performed using a 50 kV, 100 mA, 60 Hz power supply as the excitation source. To detect the PD events, a Doble PD Smart with HFCT-300 sensor was used [65]. The Doble PD Smart complies with IEC 60270 and VDE 0434, among other standards [65]. PD signals at frequencies from 35 kHz to 20 MHz and an apparent charge as low as 0.2 pC can be measured [65].
PD tests were performed on a patterned, 1-mm thick AlN-DBA substrate. The spacing between metal traces and from the metal traces to the edge of the ceramic was 2 mm. The following three cases were tested: 1) a single substrate; 2) two stacked substrates with the middle metal connected to the source ground; 3) two stacked substrates with the middle metal connected to half of the applied excitation voltage. Each case was tested under two conditions: 1) S1D2 = D1 (the high-side switch is conducting and the low-side switch is blocking), and 2) S1D2 = S2 (the high-side switch is blocking and the low-side switch is conducting).
First, the PD tests were performed with the samples in air to have a high signal-to-noise ratio. These tests revealed that, as was shown in the electrostatic simulations, the PD for the DBA substrates will occur at the triple points. Specifically, the PD will take place along the edge of the metal pad where the high potential is applied. The resulting PDIV for the cases when the samples are tested in air are listed in Table II. When S1D2 is equal to D1 (the applied voltage), and the middle metal is connected to half of the applied voltage, the PDIV increases by 53% compared to the single-substrate case [64]. The same increase in PDIV was observed when S1D2 is equal to S2 (ground). These results, which are in good agreement with the simulations, demonstrate that connecting the middle metal to half of the applied voltage gives predictable, consistent results for both switching states.
Since the power module will be encapsulated, PD tests were also performed on a stacked substrate sample that was encapsulated with SilGel 612 from Wacker. For this sample, the S1D2 potential was connected to S2 (the worst case). The measured PDIVs for this sample are listed in Table II. When the middle metal is connected to the source ground, the PDIV is 7.4 kV rms (10.5 kV peak). For this same case, breakdown occurred at 8.5 kV rms (12.0 kV peak). This means if the middle metal is connected to ground, or if a single substrate is used, then there is 20% margin between the peak breakdown voltage and the voltage rating of the 10-kV SiC MOSFETs. When the middle metal is connected to half of the applied voltage, no PD could be measured up to 10.5 kV rms (14.8 kV peak). The testing was stopped at 10.5 kV rms due to the reduced signal-to-noise ratio. This suggests that encapsulated stacked substrates with the middle metal connected to half of the applied voltage will have more than a 40% higher PDIV compared to a single substrate or a stacked substrate with the middle metal connected to ground. Therefore, it is advantageous to use the stacked substrate structure with the middle metal connected to half the applied voltage to increase the high-voltage performance of the power module.

VII. CONCLUSION
This work proposed a high-density power module for 10-kV SiC MOSFETs with reduced CM current and electric field strength. The optimal layout and system interface enable the module to switch 5 kV in tens of nanoseconds with negligible ringing and voltage overshoot. This is the fastest switching speed reported to date for 10-kV SiC MOSFETs. To reduce the adverse EMI effects of this high-speed switching, a CM screen was incorporated into the power module design. This screen was realized by stacking two DBA substrates and connecting the middle metal to the midpoint of embedded decoupling capacitors through vias and metal posts. This proposed method creates a low-impedance path at high frequency, and contains the current that would normally flow to the system ground within the power module. With this screen, the measured CM current leaving the power module decreases by ten times. This proposed integrated screen will reduce the need for filtering at the system level, thereby increasing the power density, lowering the cost, and simplifying the design of power electronic systems. Moreover, it will permit the operation of the 10-kV SiC MOSFETs at faster speeds, thereby reducing losses and increasing efficiency.
This screen also increases the voltage rating of the power module. PD tests showed that stacking two substrates and connecting the middle metal to half of the applied voltage increases the PDIV by 53% compared to a single substrate. When testing two encapsulated stacked substrates with the middle metal connected to the source ground, breakdown occurred at 8.5 kV rms (12.0 kV peak). This breakdown voltage limits the voltage rating of the package. When the middle metal of the encapsulated substrates is connected to half of the applied voltage, the PDIV exceeds 10.5 kV rms. This method for reducing the electric field is effective and simple to implement, and will enable high-voltage packages with greater power density.

ACKNOWLEDGMENT
The authors would like to acknowledge the experimental assistance from K. Li and Y. Xu. The authors also acknowledge the assistance of Dr. X. Feng and the Center for Electromechanics at the University of Texas at Austin in conducting the partial discharge tests. The substrates used in the power module prototypes were donated by DOWA, and the external decoupling capacitors used for the switching tests were donated by Electronic Concepts. This work was conducted with the use of ANSYS Maxwell 2D, ANSYS Maxwell 3D, and ANSYS Q3D Extractor, donated in-kind by Ansoft Corporation of the CPES Industry Partnership Program. He developed innovative assemblies for power electronic packaging in the INSA de Lyon. He worked then as a Research Fellow in the field of materials science and engineering in Lyon, where he elaborated nano-scale microstructure stainless steels for nuclear power plants and an intrinsic microstructure investigation for heated copper. In 2014, he joined the Power Electronics Machines and Control Group in the University of Nottingham, Nottingham, U.K., where he is currently working as a Research Fellow. His current research interests include integration, materials science aspects of interconnect technologies, packaging, thermal and thermo-mechanical simulation and reliability of high-performance packaging technologies for wide bandgap power devices for a number of UK EPSRC, EU, and industry-funded projects. He has published several research journal and conference papers on these topics. He is the Director of the U.K. Engineering and Physical Sciences Research Council (EPSRC) Centre for Power Electronics, which combines the U.K.'s best academic talent to address the key research challenges underpinning power electronics innovation plasma applications. He holds two patents.
Dr. Johnson is an Associate Editor of the journal Earth, Moon, Planets.