Fast and Accurate Multi-Physics Model for Optimization-based Design of VSBBC

The development and validation of an advanced two-level Voltage Source Back-to-Back Converter model, considering its multi-physics operation, is presented in this paper. Based on a set of input parameters, the proposed model evaluates the converter in terms of input current ripples, transient performance, losses, and total volume. The model is discussed separately in three parts: modulation and control analysis, semiconductor loss estimations and heatsink sizing, and passive components sizing, i.e. for the boost inductors and DC-link capacitor. The performance analysis and loss calculations are verified to be accurate using time-domain simulations and experimental loss measurements. Due to its computational efficiency and accuracy, the proposed model is suitable for use within an optimization design environment.


I. INTRODUCTION
To maximize a specific feature or performance, modern system design typically involves an optimization process [1]. In power converter design, the performance indices are often identified as volume, weight, cost, and power loss [2].
Considering the multi-disciplinary nature of power converter operations, its performance is often evaluated using different finite element models. Despite their accuracy, the challenge with this approach lies in its complexity and demand for high computational resources. During an early design phase, analytical models are usually preferred as they are more computationally efficient.
In [3] and [4], systematic modelling approaches are introduced for different three-phase AC-AC converter topologies, with an emphasis on comparing their efficiency and power density. On the other hand, several DC-DC converter topologies are compared in [5], with a modelling framework that also considers cost as a performance criterion. In [6], component models for a three-phase two-level DC-AC converter system are proposed and employed within a system level design tool that optimizes power density.
In motor-drive applications, a widely used converter for AC-AC power conversion is the two-level Voltage Source Back-to-Back Converter (VSBBC) topology [7], as depicted in Fig. 1(a). Despite its popularity, there are only a handful of publications targeting its modelling and design. This paper proposes a comprehensive two-level VSBBC model, as shown in Fig. 1  III. CONVERTER ANALYTICAL MODELLING The converter analytical model is described separately in three: 1) modulation and control, 2) losses and thermal management and 3) sizing of passive components.

A. VSBBC Modulation and Control
In this section, converter modulation and the employed control strategies are considered.

1) Modulation and Current Analysis
Modulation is the process of switching semiconductor devices within a power converter from one state to another. The basic operation and electrical properties of the VSBBC are significantly determined by its modulation parameters, i.e. modulation index, switching frequency, etc.
Standard modulation schemes are mostly either continuous, such as the symmetrical Space Vector Modulation (SVM), or discontinuous, e.g. DPWM1 [9]. Fixed switching frequency pulse width modulation (PWM) enables a mathematical representation of the power converter operation, not included here for the sake of brevity [9].

a) Device Average and RMS Currents
The mathematical analysis of converter modulation allows average duty-cycle references over switching period ℎ, ( / ) to be calculated and average device currents / over switching period, can be determined using (2).
where ℎ is the instantaneous phase current and is the electrical angle. Subsequently, average and rms device currents over fundamental period ( / , and / , ) can be computed as in (3) and (4). and / , are derived for different modulation schemes, allowing them to be written as a function of modulation index, peak phase current value, and power factor.

b) Maximum Input Current Ripple
When connecting the AFE rectifier to the grid, boost inductors attenuate the switching ripples present in the input current waveform to ensure power quality compliance with industry standards. These switching ripples are caused by discrete changes in the voltage drop across the boost inductors and at any point in time, peak-to-peak current ripple can be calculated as in (5).
where is the voltage drop across the inductor applied over a continuous 'turn-on' period of .
To simplify the analysis, phase a current ripple at reference voltage angle = 0° is considered to be maximum. This simplification is justified as inductors are often designed near saturation limits. For a unity input power factor operation, = 0° corresponds to phase a peak fundamental current, when drop in from its nominal value, due to magnetic saturation, is expected to be most significant. Consequently, this leads to current ripples typically being largest.
At 0 ∘ reference vector angle, is calculated as in (6).
where ̂ is the voltage magnitude when switches , , and from Fig. 1 are turned on, and ̂ is the magnitude of input grid voltage. As determined by the modulation sequence, is /2 for symmetrical SVM and for DPWM1, where duty-cycle at 0 ∘ can be calculated from (7).
where is the modulation index.

c) DC-link Capacitor RMS Current
For appropriate thermal sizing of the DC-link capacitor, its rms current , is calculated using the analytical method in [10]. For each converter, , is calculated as in (8), assuming a sinusoidal AC current and constant DC-link voltage, neglecting high frequency switching components.
where is the modulation index and is the AC side power factor angle. In this work, the worst-case rms current on the VSBBC DC-link capacitor , (worst) is considered to be an average of current ripple harmonics from the AFE and VSI. This is a conservative approach as with appropriate synchronization, their current ripple harmonic contributions can be made to cancel out each other [11].

2) Control of VSBBC
The simplicity and robustness of a standard VSBBC control, due to its two-stage conversion, makes it an attractive topology compared to direct AC-AC power conversion topologies [12]. Independent cascaded control schemes are employed for the AFE and VSI, as illustrated in Fig. 2 and Fig. 3. The VSI controller aims to regulate the machine torque and speed while the AFE controller is responsible for maintaining unity power factor at the grid terminals and tracking the DC-link voltage reference.

a) DC-link Voltage Overshoot
In a VSBBC operation, the DC-link capacitor acts as an energy damper that absorbs or supplies power during output load transients. During a worst-case load transient, which is defined as an externally triggered step removal of rated load, the AFE d-axis current reference reacts immediately with the help of a feed-forward power signal, also shown in Fig. 3, causing the AFE controller output to saturate. When this happens, energy stored in the boost inductors continue to flow into the converter, causing the DC-link voltage to rise (or 'overshoot').
To calculate the maximum DC-link voltage overshoot , during this period of time, the boost inductors and DC-link capacitor can be considered as an uncontrolled, second-order LC-circuit. Thus, , is calculated as in (9).
where ̂ is the peak grid input voltage and 0 is the output load power that is abruptly removed. It is important to note that these calculations do not account for delays due to sampling and PWM. In practice, , is expected to be slightly higher than calculated in (9).

B. Semiconductor Losses and Heat-sink Modelling
Semiconductor switching devices account for a large portion of the overall VSBBC losses and an adequate cooling system must be in place to dissipate these losses [13]. Semiconductor loss models and a simple heat-sink sizing model is described in this section.

1) Semiconductor Losses
Semiconductor losses are typically considered separately as conduction and switching losses. Conduction losses occur during the device 'on-state' and are calculated with device average and rms currents from (2) and (3), as in (10).
where and are device forward drop and 'on-state' resistance obtained by linearizing the manufacturer-provided 'on-state' conduction characteristics about the peak current. On the other hand, switching losses occur during switching transitions and are a function of the instantaneous switching energy dissipation and switching frequency , as in (11).
The dependency of on / can be found in the manufacturer data sheet while its dependency on can be modelled based on recommendations from [14].

2) Semiconductor Heat-sink Modelling
For devices housed inside a power module, a two-node Lumped Parameter Thermal Network (LPTN) is employed to describe its thermal behavior. This simplified approach assumes that heat energy is dissipated only in one direction and that devices share the same junction temperature. For a maximum steady-state junction temperature , , the maximum cooling system thermal resistance ℎ, , can be calculated as in (12).
where is the ambient temperature, is the total semiconductor losses, and ℎ, is the junction to heat-sink surface thermal resistance.
A forced-air convection cooling system model is developed based on commercially available LA series cooling systems from Fischer Electronics and theoretical relationships in [15]. For a fixed height and length-width ratio, a cooling system's thermal resistance can be expressed as a function of volume as in (13). where coefficients 1−3,ℎ are found by performing a curvefit on manufacturer data. Fig. 4 shows a plot of the volume against thermal resistance relationship for the LA series cooling systems obtained using (13) and compares it against   that for customized heat-sinks with a Cooling System Performance Index (CSPI) of 17.7W/Kdm 3 reported in [15].

C. Passive Component Modelling
Besides the semiconductor heat-sink, passive components also contribute to a significant portion of the total converter volume. For a VSBBC system, the main passive components are boost inductors and the DC-link capacitor, which sizings are discussed in this section.

1) Boost Inductor
The soft saturation characteristics of toroidal powder cores makes them an appropriate choice for boost inductor applications. These cores are usually designed assuming thermal, geometrical, and magnetic constraints: 1. Thermal constraints: a minimum wire diameter , is needed for acceptable winding losses and temperature. 2. Geometrical constraints: a maximum number of winding turns , is set based on the available inner core window area. 3. Magnetic constraints: the powder core material permeability drop characteristics determines the maximum magnetic force allowable in the core, to limit permeability drop due to saturation.
To design the toroidal core inductor, manufacturer data of commercially available cores of a selected material are first compiled into a database. From this data, nominal inductance factor 0 allows the required number of turns for inductance to be calculated for each core: where is the permeability drop, which can be initially set as 1. Next, the resulting magnetic force in the core can be determined as in (15).

= (15)
where is the magnetic path length, and is the rms inductor current. Based on , a new can be interpolated from the core material permeability drop characteristics and brought into (14) to calculate a new . The process is stopped after a few iterations and the final design is evaluated against , and constraints.
With the Mega Flux 60 core material (Chang-Sung Corp.) volume of smallest core designs, which are feasible, is plotted against inductance and current in Fig. 5. In this figure, the circled dots represent core designs with the highest inductance-current product per volume / . Assuming a thermally limited design with fixed magnetic properties, minimum inductor volume can be modelled as in (16).

2) DC-link Capacitor
For DC-link applications, polypropylene film capacitors are favorable due to their low dielectric loss tangents and better current ripple tolerances. In this work, manufacturer data for film capacitors of the same material and topological shape are compiled and fitted into a volume model [16], This volume model is based on energy storage requirements and is a function of capacitance and voltage , as shown in (17). , ( , ) = 1, 2 + 2, + 3, + 4, (17) where parameters 1−4, are estimated by performing a least mean-square approximation method on manufacturer data.
Meanwhile, minimum capacitor volume, due to thermal constraints, is modelled as in (18).
3/2 (18) where is the capacitor's equivalent series resistance, is the heat dissipation per area, and is estimated also by performing a least mean square approximation on manufacturer data.

Lastly,
, and , ℎ are compared and the larger value is determined as the required capacitor volume.

IV. MODEL VALIDATIONS
The converter modulation and control analysis is verified using a time-domain simulation study [17], while semiconductor loss models are validated with loss measurements for a prototype hardware converter. As heatsink and passive component sizing models are based on commercial products, no further verifications are performed.

A. Time-Domain Simulation Study
The simulations are carried out for a VSBBC driving a PM machine using the PLECS standalone tool and parameters for the study are listed in Table I [18].  Subsequently, the VSI is enabled at t=0.2s at it also controls machine speed to a reference value of 1500rpm. At t=0.3s, load torque of 8.5Nm is added to the machine and the converter controls respond instantly to maintain DC-link voltage and speed. Due to the limited bandwidth, a slight dip in rotor speed and DC-link voltage results. Finally, load is removed in a step at t=0.4s, simulating a trip of the VSI converter (worst-case transient).
Under rated torque and speed operation, input phase a current can be seen in Fig. 6(b). The peak-to-peak current ripple at 0° reference voltage vector is determined in the converter analytical model as 2.50A, matching well with the simulation which gives 2.44A. The capacitor current is also shown in the figure. The capacitor rms current calculated in the model to be 4.48A while in the simulation it is 4.45A, also revealing a good match. At t=0.45s, when the load is removed, the simulated voltage overshoot and saturation of modulation index can be seen in Fig. 6(c). The converter analytical model computes a maximum overshoot of 202.30V, while the recorded value in the simulation is 203.61V. The small differences are due to PWM delays in the switching model.

B. Experimental Analysis
To experimentally verify the loss and heatsink thermal model, a prototype converter was built. The semiconductor devices are realized with an Infineon FS50R12KT4B15 power module, which is directly mounted onto a Fischer Electronics LA6 cooling system. Device junction temperatures are measured via NTC thermistors integrated within the power module.
The converter is operated as a VSI to power a resistiveinductive load ( ℎ = 3 , ℎ = 5.3Ω). Converter losses are measured at various DC-link voltages, switching frequencies and currents using a Kinetiq PPA2530 precision power analyzer. Results from the measurements are shown in Fig. 7.
Initially, loss estimations from the model were found to be significantly lower than measured values. There are several reasons to this: firstly, parasitic DC-link and emitter inductances in the commutation circuit greatly affects switching losses and consequently, real switching energy dissipate in the implemented circuitry can differ from the datasheet specifications. Secondly, the effect of junction temperature on switching losses is not accounted for in the model. Lastly, contact and cable resistances in the test setup can add to the ohmic losses measured.
To take these factors into consideration, device switching energies from (11) are corrected by a factor of 1.5 and ohmic losses due to extra contact resistances of 0.05Ω are included in the model. The corrected loss model, as can be seen in Fig.  7, is significantly more accurate in predicting the converter losses.
To verify the thermal models, the cooling system's thermal resistance is calculated as in (19).
where ℎ, is the junction-to-baseplate thermal resistance provided by the device manufacturer, is the junction  temperature measured using the internal thermistor, and ℎ is the heatsink surface temperature measured with a thermocouple. A thermal resistance of 0.25 K/W is obtained from the analytical thermal model, while experimentally it is calculated to be 0.28 K/W. This is a reasonable match considering the simplifications made in the thermal model.
V. CONCLUSIONS This paper presented an advanced VSBBC model to evaluate its electrical performance, semiconductor losses, and total volume. Time-domain simulations of the converter verified that the modulation and control analysis is accurate. Further, losses measurements were performed on a prototype converter to validate the semiconductor loss and thermal models. Due to its simplicity, the proposed model allows a quick and accurate evaluation of the converter, and it can be easily combined with machine models for a holistic optimization of motor drive systems.