A New Capacitor Voltage Balancing Method for Trapezoidal Operation of Modular Multilevel DC-DC Converters

In this paper, a new submodule (SM) capacitor voltage balancing algorithm is proposed for the trapezoidal operation of a Modular Multilevel DC-DC converter (MMC-DC-DC) for HVDC/MVDC. Trapezoidal wave-shaping leads to SM switching at fundamental frequency, making the balancing process more challenging. In the proposed method, balancing is achieved by controlling the equivalent duty-cycle of each SM. This control is made possible by the exploitation of the ramps in the trapezoidal voltage waveforms, that allow to impose an uneven power flow in the different SMs. The proposed balancing has been validated in PLECS simulation for a 10MW, 20kV 20kV MMC-DC-DC converter.


Introduction
High voltage DC/DC converters are gaining importance in high voltage direct current (HVDC) and medium voltage and direct current (MVDC) systems when multi-terminal network topologies are considered that inevitably require interconnection of systems at different voltages. In addition, large and medium scale renewable energy sources, e.g. wind and photovoltaic, can be arranged in a DC collector that is then interfaced to an HVDC network through a high-voltage high-power DC/DC converter. For both these application examples, DC transformers have been under investigation by many researches last decade [1] [2]. In recent years, the focus in the development of high power converters has been more on the voltage source converter (VSC-HVDC) for AC/DC conversion, since the introduction of the MMC [3] and the breed of modular multilevel topologies that followed. However, several DC/DC converters based on the MMC concept have been recently proposed for both multi-terminal HVDC applications and integration of renewable sources into the HVDC grid. A detailed review of the most promising topologies such as the MMC-DC-DC converter with sinusoidal operation and with trapezoidal operation, the Controlled Transition Bridge converter (CTB), the Alternate Arm MMC-DC-DC converter and the modular multilevel DAB converter (MMDC) can be found in [4] [5] [6]. This paper will consider the MMC-DC-DC converter under trapezoidal operation with a focus on the development of a new capacitor voltage balancing method. Fig. 1 shows the MMC-DC-DC converter where two MMCs with half-bridge SMs are connected front to front through a medium frequency, three phase transformer.
In [7], the MMC-DC-DC arms are modulated with the trapezoidal waveforms (V arm ) shown in  This AAC-like operating mode will not be further considered in this work, and only conventional MMC operation, with both arms always conducting with trapezoidal modulation, will be considered. In such a modulation, the SMs in each arm are either all inserted or all bypassed in the time intervals corresponding to the maximum and the minimum values of the trapezoidal wave-shaping. Referring to Fig. 2, it is easy to see that if T t = 0 all the SMs would be inserted/bypassed with a 50% duty cycle (g i = 0 if SM i is bypassed, g i = 1 otherwise), with no margin of action for capacitor balancing.
Instead, the presence of the ramps allows a degree of control since the switching order during the ramps can be varied according to the balancing needs. To this purpose, a dual phase shift is proposed in [8] to balance the capacitor voltages that can only be applied when the generated AC phase voltages have three levels. Therefore, it is only appropriate for MVDC applications with a very limited DC voltage gain. Instead, in [6], fixed gate signals shifted by an angle θ are used to generate the trapezoidal waveforms. Because of the shift between the gate signals, different arm currents flow through each SM capacitor and the net charge can be varied to control voltages. Balancing is achieved by assigning gate signal which causes higher net charge to the capacitors with lower voltage. A similar principle is used also in the balancing algorithm proposed in this paper, with the difference that the duty-cycles of the SMs are changed to achieve capacitor voltage balancing. In comparison to the fixed gate signals method, the balancing is achieved faster with this method since with higher duty cycle, higher net charge can be achieved and assigned to the submodule capacitors with lower voltage. This results in a more intuitive and easy to implement solution, whilst can effectively guarantee balancing. To simplify the analysis and the drawings, the rest of the proposed analysis will use N P = 4 SMs for each arm in the primary MMC and N S = 3 in the secondary. However, N P and N S can be modified to any number based on the power requirement and

Fig. 3: Primary Arm Voltages and Primary Transformer mid-point Voltage
Each multilevel arm voltage waveforms can be generated using two approaches. The first method is by modulating the series connected submodules with the fixed 50% duty cycle gate signals which are shifted  Fig. 2 [6]. Instead, in the second approach the duty-cycle of each gate signal which is used to modulate the series connected submodules is varied where the maximum duty-cycle is π + (N − 1)θ and it reduces by 2θ until it reaches the minimum of π − (N − 1)θ. The capacitor balancing algorithm proposed in this paper exploits the different duty-cycles of the SMs to redistribute charge and guarantee accurate voltage control. Fig. 5 shows the gate signals and the produced multilevel voltage waveform for V armUA when different duty-cycles are used.  The primary and secondary transformer phase voltages (V aT p and V uT s ) shown in Fig. 6 are shifted by a voltage angle ϕ which determines the amount of power flow between MMCs. From the voltages, the current flowing in the transformer -and in the primary and secondary MMC arms and in the inserted capacitors -can be derived analytically. The general equation for phase a on the primary side takes the form of equation 1, where α is the angle in Fig. 6. The voltage across the leakage inductance, V Lk , can be found by subtracting V uT s from V aT p . Starting at point 0 in Fig. 6 where α = 0 the equation of V Lk for each interval during π can be found and the primary phase current, i aT p(α) , can be determined for each section using equation 1 as shown in table I where ρ is the dc voltage gain (ρ = n * V S V P ), ζ = 3 * L k * ω s , ω s is the angular frequency and L k represents the leakage inductance of the transformer. Finally, n is the transformer turn ratio. Since i aT p(α) is a symmetrical waveform and has no dc offset, therefore i aT p(0) = −i aT p(π) and I aT p0 can be calculated as shown in equation 2. (2)

Proposed SM Capacitor Voltage Balancing
The analysis of the balancing method is discussed only for the upper arm of phase a of the primary MMC. Fig. 7 shows the upper arm current of the primary MMC, I UA , with the gate signals for the corresponding SMs, generally different from 50%. Each capacitor will be charged/discharged only when the its gate signal is high and the net charge ∆Q in each capacitor will depend on the operating point and on the duty-cycle of each SM. The net charge ∆Q of each capacitor can be calculated analytically by taking the time integral of the arm current I UA during the period where its gate signal is high. Moreover, similar to the analysis for a conventional MMC [9], the arm current comprises half of the AC phase current and the circulating current which can be calculated based on equation 3, where the average output power, P out , is obtained from the current (i aT p(α) ) and voltage equations as shown in equation 4. Knowing the arm currents, the analytical expression of the charge variation in each SM capacitor can be found, as shown in equation 5.
As it can be seen, the sum of ∆Q UA1 to ∆Q UA4 is zero and it is well known that the subomdule voltage is ∆V c = 1 C ∆Q. Therefore, the sum of ∆V cUA1 to ∆V cUA4 will be zero and this proves the balance between upper and lower arm voltages. It can be also observed that the ∆Q UAi is a function of ρ, θ, ϕ, and the duty cycle of gate signals, represented by the index i, where i = 0 indicates the lowest duty-cycle. Under steady state operation ρ, θ cannot be modified and ϕ is selected based on power flow requirement. Therefore, the only factor that can be changed to balance the capacitor voltages is the duty-cycle assigned to the different SMs. In case of power flowing from primary to secondary, the balancing can be achieved by assigning the highest to the lowest duty cycle gate signals to the ascending sorted submodules. The block diagram in Fig. 8 shows the implementation details of the new capacitor balancing approach. 2 π 2 π -3 θ 2 πθ 2 π -2 θ π π -3 θ πθ π -2 θ

Simulation Results
To verify the proposed balancing method, a 10MW, 20kV-20kV MMC-DC-DC converter model has been implemented in PLECS. The circuit parameters are shown in Table II. Results show that the capacitor voltages are balanced at nominal value (1kV) with 10% ripple as presented in Fig. 9