Experimental Validation of a Quasi-Z-Source Modular Multilevel Converter With DC-Fault Blocking Capability

This article considers the design methodology and the modulation of the quasi-Z-source modular multilevel converter (qZS-MMC) with half-bridge submodules (HBSMs) and evaluates its performance in the voltage boosting mode for medium voltage applications. The qZS-MMC consists of two qZS networks inserted between the two terminals of the dc input source and the dc-link terminals of an MMC, which allows the generation of an output voltage larger than the input dc voltage. Two modulation schemes have been analyzed based on a mathematical derivation for the converter internal voltages, currents, and stored energy. The qZS circuit is proven to provide the qZS-MMC with HBSMs to deal with dc faults. The experimental results validate the performance of the proposed modulation schemes and the dc-fault blocking capability of the qZS MMC. Finally, the losses of the qZS-MMC are compared against a standard MMC using full-bridge submodules that can also provide dc-fault capability. The range in which the qZS-MMC is more efficient has been identified. Furthermore, the qZS-MMC can provide a significant reduction in a number of semiconductor power devices with the same performance.


I. INTRODUCTION
E LECTRIC power systems are seeing an increasing penetration of embedded generation, especially for renewable energy resources, such as wind turbines and photovoltaics [1]- [4]. The output voltage of most renewable energy sources fluctuates in a wide range with changes in the operating conditions. Therefore, having a power converter that can compensate for these fluctuations by being able not only to perform the more common voltage step-down but also to step-up the voltage is desirable. Recently, a great attention has been paid to the modular multilevel converter (MMC) in both medium-and high-voltage applications due to its advantages of scalability, modular design, redundancy, and better harmonic performance [5]- [9]. The basic building block in an MMC is The HBSMs are widely used to build the MMC [10], [11]. However, an HBSM-based MMC is unable to deal with dc fault [12], thus depending on fast circuit breakers to isolate dc faults. In addition, the peak value of the fundamental phase voltage is limited to one-half of the total dc-link voltage levels (step-down operation). Therefore, the MMC with HBSMs must be upgraded with additional hardware to withstand the dc-fault currents and is considered inappropriate for interfacing many renewable energy sources to ac grid systems as it only works as a step-down converter. To overcome these shortcomings, using FBSMs instead of HBSMs has been proposed [13]. The resulting converter has an inherent dc-fault blocking capability as the FBSMs can insert both voltage polarities in the arm and block the overcurrent caused by shortcircuiting the dc bus. Also, the output voltage range can be extended above the half value of the dc-bus voltage. These features are a result of the capability of the FBSMs to generate not only zero and positive voltage states as the HBSMs but also a negative voltage state. The FBSMs require as twice as many IGBTs as the HBSMs, which not only increases the converter cost but also significantly increases the total power losses because the SM current flows through two IGBTs instead of one with the HBSMs [13].
An interesting solution can be achieved by combining HBSMs and FBSMs, where depending on the ratio of the FBSMs to HBSMs, the dc-fault blocking and the voltage stepup capabilities of the FBSM-based MMC can be obtained [14]. For ratios that are equal to or higher than 1:1, the converter can block dc faults. The ratio should be equal to or higher than 2:1 to extend the output voltage range (voltage stepup). This hybrid MMC has a limitation in its operation, where the boosted output voltage should not exceed a specific value as this causes a capacitor voltage imbalance problem between the FBSMs and HBSMs. To clarify that, FBSMs can charge or discharge regardless of the arm current direction, while HBSMs can charge (discharge) only during positive (negative) state of the arm current. At a specific operating point, the negative current becomes insufficient to make the HBSM to discharge, which will lead to a steady voltage increase of the SMs capacitors of the HBSMs. It was reported in [14] that the maximum output voltage is restricted to 1.63 times the half value of the dc-link voltage at a unity power factor. 2168-6777 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
Due to the difficulties associated with the FBSM-based MMC and the hybrid MMC, a new approach based on integrating the impedance network concept [15]- [18] with the HBSM-based MMC proposed in [19], namely the quasi Z-source MMC (qZS-MMC), is proposed in this article. The qZS-MMC has the capability to step up the output voltage and to block the dc fault, which is achieved by connecting the qZS capacitors with opposite polarity to the direction of the fault current. Two modulation schemes have been proposed in [20] and [21] focusing on the operation principles and derivation of the switches stress voltage. However, neither systematic design guidelines nor estimation of the capacitor stored energy/size has been provided in [20] and [21]. Therefore, the two modulation techniques have been analyzed in detail and validated experimentally in this article.
This article has been organized as follows. Section II presents the operation principles of the proposed qZS-MMC. The proposed modulation schemes are illustrated in Section III. Section IV provides a guideline for the capacitors and inductor design. Section V investigates the dc-fault blocking capability. The experimental studies are provided in Section VI to demonstrate the performance of the proposed converter. To highlight the advantages of the proposed converter, a comparison between the proposed converter, the MMC with FBSMs, and the qZS cascaded multilevel converter is carried out in Section VII in terms of the required number of the passive and active components, total conduction and switching power losses, and output voltage quality under similar input and output voltages and power levels. Finally, Section VIII concludes the work done in this article.

A. Circuit Configuration
The structure of the single-phase configuration qZS-MMC is shown in Fig. 1. The MMC leg consists of the upper and the lower arms. Each arm is formed by N S M seriesconnected identical SMs, and an arm inductor (L O ). Each SM is based on a half-bridge inverter configuration with one dc-link floating capacitor. The two switches (S 1 and S 2 ) in the SM are controlled by a single state and its complement. When S 1 is ON, the SM capacitor is bypassed, and the SM terminal voltage is zero. If S 1 is OFF, S 2 is ON; therefore, the voltage inserted by SM in the arm is equal to the SM capacitor voltage. Only during this latter active state, the capacitor gets charged or discharged according to the direction of the arm current [22], causing one of the limitations associated with the HBSMs.
The qZS stage consists of two identical qZS networks, which are inserted between the dc source (V dc ) and the MMC leg (or three-phase legs), as shown in Fig. 1, where a single-phase configuration is shown. The two networks share a midpoint node "O" between the two capacitors C U 1 and C N1 that can be used as a reference point for the output voltage v Ao .

B. Summary of MMC Operation Principles
The desired ac output voltage is generated by changing the number of inserted SMs in each arm. The instantaneous voltage of the upper and the lower arms and the upper and lower dc-link voltages is denoted by respectively. By applying Kirchhoff's voltage law in Fig. 1, the ac output voltage is given by Assuming the direction of i U A and i N A is shown in Fig. 1, and the arm currents can be expressed by where i cir represents the circulating current in the arm. This current i cir contains a dc component I U N that provides the actual power transfer and ac components, which usually contain even low-order harmonics, with the second-order one being the most significant. The circulating current i cir and the second-order harmonic component i 2 f can be calculated by

C. Summary of qZS Operation Principles
Similar to impedance-network circuits [17], the operation of the qZS requires the introduction of the short circuit [shoot through (ST)] at its output terminals in order to increase currents and consequently the energy stored in the qZSnetwork inductors, which is later transferred to the qZSnetwork capacitors. This stored energy provides the voltage boosting capability [15].
It is difficult to use the MMC leg to produce the ST by bypassing all the SMs in both the upper and lower arms due to the presence of the arm inductors in the path of ST current. The ST path should have a low inductance. Even with the assumption that the arm inductors could be removed, bypassing all the SMs would lead to a drop in upper and lower arm voltage levels to zero, which would cause a high distortion in the output voltage and the benefit of having a multilevel functionality will be compromised. To prevent this, two chain links of series-connected switches S U and S N able to handle half the dc-link voltage are connected at the upper and lower qZS-network end terminals, respectively, to provide ST current path to the dc-link midpoint "O," as shown in Fig. 1. The number of the series switches in each chain link will be at least equal to the half number of SMs in each arm, assuming an equal voltage rating with the SM switches. Generally, there are two operation modes for the qZS network [15]. Considering the upper qZS network that is shown in Fig. 2(a), the operation modes are follows.

1) ST Mode:
The dc-link terminals are shorted, which forces the series diode to become reverse biased, as shown in Fig. 2(b). Hence, the stored energy in the capacitors begins to transfer into the inductors.
2) Non-ST (NST) Mode: The qZS network is connected to the inversion stage then the series diode will be forward biased, as shown in Fig. 2(c). The stored energy in the inductors begins to transfer to the load, and qZS capacitors begin to charge.
During these switching modes, the SM capacitor is charging or discharging depending only on the arm current polarity, where the SM capacitor voltage decreases (increases) when the corresponding arm current is negative (positive) regardless of the switching modes.
Assuming that the qZS components are identical where where D sh is the ST duty ratio. Turning on any of the chainlink switches S U or S N causes distortion in the output voltage levels, which needs to be corrected by the SMs of the MMC stage using a suitable modulation technique, and this will be further investigated in Section III.

III. PROPOSED MODULATION SCHEMES
This section describes the proposed modulation schemes for the qZS-MMC. The following assumptions were made when analyzing the operating principles of the qZS-MMC.
1) The qZS-MMC operates in the inversion mode.
2) The SM capacitor voltages in each arm are well balanced [22].
3) The ac-circulating current is suppressed at a negligible level [23]. 4) The power losses of the converter are ignored. In this article, the phase disposition (PD) carrier technique is employed for the MMC with two opposite reference modulating signals for both the upper and the lower arm SMs. Assuming N S M SMs are used per arm, N S M level-shifted carriers are required, and consequently, a (2N S M + 1) level waveform is generated in the output. Each carrier is responsible for producing the gating signals of two SMs: one from the upper arm and one from the lower arm, which are chosen according to a capacitor voltage balance algorithm [22]. Through a switching frequency period, the total number of inserted SMs in the phase-leg is changed between N S M − 1, N S M, and From (1), the instantaneous value of the output voltage is reliant on the upper and lower dc-link voltage potential and the voltage generated by each arm. In the traditional MMC, the dc-link voltage potentials v U O and v O N are generally equal to half of the dc-source voltage, which means that the second term in (1), which represents the common-mode voltage, is always zero. In a qZS-MMC, the operation of each of the chain-link switches (S U , S N ) alone will generate a large common-mode voltage that will seriously disturb the output voltage v AO . This disturbance can be avoided by firing both chain-link switches simultaneously. This mechanism is called the "simultaneously shorted (SS)" technique, which has been proposed in [20]. Another option is to compensate the disturbance caused by any of the chain link by having the arm generating an adapted voltage to compensate the disturbance in the output voltage, as suggested in (1). This principle can be implemented by changing the number of the inserted SMs in the corresponding arm and is referred to as the "reduced inserted cells' (RICs)" technique [21].

A. SS Technique
In this technique, the upper and lower chain links S U and S N should be shorted simultaneously. Considering that both upper and lower qZS networks operate in the NST mode, the upper dc-link voltage v U O will be equal to the lower dc-link voltage v O N and both equal to v U N /2. This means that a zero common-mode voltage which is represented by the second term in (1).
If each of the chain-link switches (S U , S N ) is conducted alone, the common-mode voltage will become extremely high at the value of half of the dc-link voltage and then the output voltage v AO will be extremely disturbed. To avoid this disturbance, both chain-link switches should be fired simultaneously where a zero common-mode voltage can be attained. This can be simply achieved by comparing the triangle carrier signal with a level D sh proportional with the desired ST duty cycle, as shown in Fig. 3. The upper and lower arm inductor voltages in the ST and NST modes, respectively, can be expressed by In (6), both v U O and v O N are equal to half of the peak value of the dc-link voltage V U N /2 defined by (4) during the NST mode. Due to the assumption that the average current in the inductor remains the same, the average voltage across the inductor over the switching period is equal to zero, and consequently, the SMs' capacitor voltage is given by From (7), the SMs' capacitors V c will be charged according to the average value of the dc-link voltage divided by N S M . The peak of fundamental phase voltage V m can be expressed by where m is the modulation index and G is the converter voltage gain, which has been defined by (9) when using the SS technique The output voltage and current are expressed by where ϕ is the phase shift between v AO and i AO , I m is the peak of fundamental phase current, and ω is the fundamental output angular frequency. As a result of switching the dc-link chain links, the upper and lower arm voltages can be expressed by Neglecting the converter power losses, the dc-link power which is a product of the dc components in the dc-link current (arm current) and dc-link voltage equals to the load active power and is given by The dc component in the arm current and consequently the average value of the qZS-inductor current can be expressed by In this technique, the chain-link switches are subjected to a high-voltage stress especially with increasing the converter voltage gain. The reason is that the SM capacitor voltages have to be charged according to the average value of the dc-link voltage.

B. RICs' Technique
The concept of introducing individual ST by gating only one of the upper or the lower chain links will create a significant drop or rise in the output voltage level. To compensate for this, the corresponding arm voltage needs to be simultaneously changed to compensate the asymmetric shorting of half of the dc-link voltage. The analysis can be derived by targeting that the SMs' capacitor is charged according to the peak value of the dc-link voltage V U N /N S M . This can be explained by considering the case of turning on the upper chain-link switches, which will cause the dc-link voltage to drop to its half, where the number of inserted SMs in the upper arm needs to be changed by N X . The arm inductor voltage v L O in ST and NST modes, respectively, can be expressed by where N U and N N are the number of inserted SMs in the upper and the lower arms, respectively, with N U + N N = N S M . Considering the average inductor voltage over the switching period is equal to zero and using (5) and (14), the additional number of SMs N X that should be bypassed is given by N S M /2. As the available dc-link voltage halves, the number of inserted SMs per leg should also be reduced by N S M /2, which makes the SMs capacitor' to charge according to the peak value of the available dc-link voltage V U N /N S M as targeted previously. To avoid the distortion of the output voltage, if the upper (lower) chain-link switches are performing a shooting through, N S M /2 SMs initially ON should be selected from the upper (lower) arm to be bypassed. During the ST intervals shown in Fig. 4(a), the number of upper (lower) inserted cells greater than or equal to N S M /2 is realized during the second (first) half-cycle of the upper (lower) arm modulating signal, as shown in Fig. 4. Hence, when the upper chain-link switches are turned on, the lower chain link will be turned off and vice versa. Considering ST carrier with unity height as shown in Fig. 4(a), the ST reference signals for the upper and the lower arms (v sh−U and v sh−N ) can be defined by To attain the average ST duty ratio over one output frequency period to be D sh , the height of ST modulating signals should be equal to 2D sh . The modified upper and lower arm The upper and the lower dc-link voltages of the qZS networks shown in Fig. 4(d) have dc and ac fundamental components. The dc-link voltage can be expressed by From (16) and (17), the peak value of the fundamental output phase voltage can be expressed by where G in case of using RICs' technique is defined by From (18), the peak value of the fundamental output phase voltage is equal to half of the peak value of the dc-link voltage.
From (2) and (17), the upper and the lower dc-link voltages and the upper and the lower arm currents have a constant/dc component and also an ac component at the output frequency. Therefore, the dc-link active power is given by where the first term of (20) is generated from the product of the dc components of the dc-link current (arm current) and the dc-link voltage. The second term is because of product of the first-order harmonic components of the upper arm current and the dc-link voltage. According to the power conversation law, the dc component in the arm current and the average value of the qZS-inductor current when using RICs' technique are given by where In this technique, since the SMs' capacitor is charged according to the peak value of the dc-link voltage, the stress voltage on the chain-link switches becomes lower than the SS technique for the same output voltage. The previous discussion is for a single-phase converter. However, for the three-phase converter, the three-phase legs are assumed to share the same dc-link connection points U and N, as shown in Fig. 1. Due to dependence of the modulating signals for S U and S N on the polarity of the output voltage phase as shown in Fig. 4 when using RICs' technique, if the upper chain-link switches are turned on, at least one of the upper arms in the three-phase legs will not be able to compensate the shorting of the upper dc-link terminals and that causes the output voltage of that particular leg(s) to decrease by maximum N S M /2 voltage levels. Consequently, a significant distortion in the corresponding output phase voltage will be generated. To avoid causing any distortion in the three-phase output voltages when using the RICs' technique, two qZS networks are required for each phase leg and are connected to the same dc-source terminals, which results in a high number of components (six qZS networks) which leads to a more expensive and nonoptimized converter. On the other hand, a half number of the SMs in each arm should be replaced by FBSMs, where the negative voltage polarity of FBSMs can be used to compensate the shorting of the dc-link terminals in case of the number of inserted SMs lower than N S M /2. This compensation mechanism is not the interest point of that article.
The S U and S N are independent of the individual phase voltages when using SS technique for the single-phase converter. Therefore, for the three-phase converter, the SS technique can be applied with only one qZS-network circuit (if the dc-side midpoint is not required).

C. Operation Constrains
As mentioned in Section II-C, the upper and/or the lower qZS-series diodes will be forward biased during the interval of the NST mode. However, during this interval, these diodes will be reverse biased if the following conditions are not achieved: where i LU, i L N, and i Ls are the qZS-inductor currents with the average value of I L . If the instantaneous value of i U A (i N A ) becomes higher than 2I L , the corresponding series diodes will be reverse biased in the NST mode. This leads to a drop in the peak value of the dc-link voltage to be V C1 instead of V C1 +V C2 and causes a higher distortion in the output voltage.
The limitation of the gain G can be deduced by substituting (2), (9), (13), (19), and (21) into (22) for both techniques (at unity m and cosϕ), which is As is clear, to fulfill the conditions in (22), the gain value (G) should be higher than 1.5. For the gain less than or equal to one (in the buck mode) and a particular range of the boost mode is 1 < G < 1.5, the diodes become reverse biased in the NST mode and the output voltage will be highly distorted. To overcome this issue, a pair of active switches is added in antiparallel with the diodes to provide a controllable path to the current in the reverse direction. Note that, the limit (23) is valid for a single-phase converter. For the three-phase configuration (two qZS networks per three-phase leg, see Section III-B), only SS technique can be applied. The gain limit is given by G ≥ 0.5 (at unity m and unity cosϕ). Therefore, the threephase converter can work properly for most of the gain range without extra antiparallel switches.

D. Control Scheme of the qZS MMC
There can be a considerable second-order harmonic component in the circulating current i cir particularly when the arm inductor size is small [23]. A proportional resonant (PR) controller G P R1 (s) [23] is applied to eliminate the second-order harmonic of the circulating current by following the undesired ac harmonic reference at the certain frequency (100 Hz) and then eliminate the steady-state error. In addition, there may be imbalance in the value of passive components of the two qZS networks and also within HBSMs, which, unless compensated, causes a circulating fundamental frequency component current leading to imbalance of voltages produced by the qZS networks and the two MMC arms, distorting the output voltage. To correct this, another PR controller G P R2 (s) is applied to minimize the 50-Hz component in the circulating current caused by passive component imbalance. Fig. 5(a) shows the control block diagram, including the two PR circulating current controllers discussed earlier.
The voltage balance control can be divided into: 1) average SMs' capacitor voltage control and 2) SMs' voltage balance control. Fig. 5(b) shows a block diagram of the average capacitor voltage control. The SMs' average capacitor voltage is calculated by the summation of the upper and the lower cell capacitor voltages divided by 2N S M , which should be controlled by reacting to the circulating current reference. The outer loop forces the average voltage of the upper and the lower arms to follow the command voltage V * C . A PI controller is used to eliminate the error between the SMs' average capacitor voltage and the command voltage V * C . This controller outputs the command for the inner loop i * cir . In addition, the SMs' capacitor voltages need to be balanced for proper operation of the MMC. The SMs' capacitor voltage balance strategy implemented here is based on the sorting algorithm method given in [22], which depends on the direction of the arm current. For positive (negative) values of the arm current, the algorithm selects the SMs with lower (higher) voltages to charge (discharge).

IV. CAPACITORS AND INDUCTORS DESIGN GUIDELINE
The capacitors account for a large fraction of the overall weight in both the SMs and the qZS networks. In this section, the expressions for the capacitance requirements for the SMs and the qZS network are derived analytically to ensure an acceptable compromise between the capacitor size and its voltage ripple. In addition, the formulas for the qZS-network inductances have been derived for both SS and RICs' technique.
A. SM Capacitors' Sizing 1) When Using the SS Technique: The passive component size calculation starts by analyzing the instantaneous power in the upper arm that can be calculated as a product of the arm voltage and the arm current. By using (2), (11), and (13), the instantaneous arm power is where S = V m I m /2 is the apparent power. By integrating (24), the arm energy stored can be expressed by To calculate the peak-to-peak energy deviation E P P , the zero-crossing points of the arm power should be calculated. There are only two zero-crossing points at θ 1 and θ 2 , which are the same as the arm current zero-crossing points. Using (2) and (13), θ 1 and θ 2 are given by where θ C is expressed by sin −1 (m cos ϕ/2). By substituting (26) into (25), E P P can be derived as The relation between the minimum capacitance value and the energy deviation E pp can be expressed by where k v is the capacitor voltage ripple factor. 2) When Using the RICs' Technique: Using (16) and (21), the arm energy variation can be derived as From (2) and (21), θ C is derived by sin −1 (m R I C cos ϕ/2). By substituting (19) and (26) into (29), E P P can be expressed by The minimum capacitance value can be expressed by From (27), it is noted that the maximum energy deviation E P P is just related to the modulation index (m) and the power factor (cosϕ) for the SS technique, while for the RICs, E P P depends also on the converter gain G. Fig. 6 shows the normalized maximum energy deviation E P P * (ω/S) versus the gain for both techniques at three values of cosϕ (0.6, 0.8, and 1) and unity modulation index. It is noted that by using the RICs' technique, a slightly reduced maximum energy deviation E P P and consequently smaller capacitor size are needed, especially when operating at increased gain. The maximum energy deviation when using RICs' technique is reduced by 20% compared with the SS technique at G that equals 2 and unity power factor.

B. qZS-Network Capacitors' Sizing
In the ST mode, the stored energy in the qZS capacitors begins to transfer to inductors, which causes the inductor currents to increase and capacitor voltages to decrease, whereas in the NST mode, the capacitors' charging and discharging depend on the value of the corresponding arm current relative to inductor current. By considering the current direction in Fig. 1 and that the qZS-inductor currents have their average value I L , the upper qZS capacitor current during the ST and NST modes is first defined by 1) When Using the SS Technique: Fig. 7(a) shows the upper qZS capacitor current waveform to illustrate its operation. Using (32) and (33), the average value of the capacitor current over a switching period is given by By integrating the capacitor current in (34) and using (13), the instantaneous value of the qZS-capacitor voltage ripple is From (13) and (34), the upper qZS-network capacitor current zero-crossing points θ 1 and θ 2 are identified as Substituting (9) and (36) into (35), the minimum qZS capacitances C U 1 and C U 2 as a function of the gain G are 2) When Using the RICs' Technique: As discussed earlier, the upper/lower qZS networks work only in the NST mode in the positive-negative half cycle of the output voltage waveform, where the capacitor current during this part of the cycle is defined by (33). The upper arm capacitor current is shown in Fig. 7(b) to illustrate its operation. By integrating (33) during the interval of NST and considering the ac component in the capacitor current, the instantaneous value of the qZS-capacitor voltage ripple can be expressed by From (21) and (34), the zero-crossing points θ 1 and θ 2 of the upper qZS-network capacitor current (34) should be identified as From (38) and (39), the minimum qZS-capacitances C U 1 and C U 2 as a function of the gain (G) can be derived by These analytical models allow to compare the capacitance of both modulation techniques and this is drawn versus the gain G and is shown in Fig. 8(a) and (b) for C U 1 and C U 2 , respectively. The capacitance values have been normalized, as noted in Fig. 8. The required qZS capacitance value for RICs' technique is higher than that for the SS technique. Due to different operating voltages that result in different voltage peaks for the capacitors in both techniques, the stored energy in each capacitor should be derived to have a fair comparison. The maximum energy deviation in qZS capacitors C U 1 and C U 2 is derived by (41) for the SS technique and by (42) for the RICs' technique The maximum energy deviation for the two qZS capacitors E CU 1 and E CU 2 is drawn versus the gain G at unity m and cosϕ and are shown in Fig. 8(c) and (d), respectively. It is noted that E CU 1 in the gain range from 1 to 2 is almost identical for both techniques but is lower for RICs' technique than the SS technique outside this gain range. The stored energy in the other qZS capacitor E CU 2 is lower for RICs technique than that for the SS technique for all gain ranges.

C. Inductors' Sizing
The design of the arm inductor was detailed previously in [24]. Therefore, this section only concentrates on the qZS-network inductor sizing. For the SS technique, the three qZS-inductor voltages during ST and NST modes are given by From (43), the three qZS inductances have been calculated as a function of gain and the switching frequency f s by where k i is the inductor current ripple factor. For RICs' technique, the source inductor voltage is given by Consequently, the source inductance L S can be calculated by The incapability of introducing ST mode for the upper (lower) chain-link switches through half the interval of the output voltage duty cycle (when N U bvor N N is lower than N S M /2, as shown in Fig. 4) makes the qZS-inductor currents hold ac component at the fundamental frequency f o . The qZS inductors (L U and L N ) have been calculated by From (44) and (46), for the same current ripple in the source inductor, the required source inductance L S when using the SS technique is higher than the RICs' technique where the inductance ratio reaches to 1.33 times at gain value that equals 2. The inductances L U and L N depend on the switching frequency f s (44) and the output frequency f o (47) for SS and RICs' techniques, respectively. It is noted that the current ripple when using SS is much lower than that using RICs' technique with a ratio 1/8 at f s = 1 kHz, f o = 50 Hz, and G = 2.

V. IMPLEMENTING FAULT BLOCKING CAPABILITY
During dc-side faults, a traditional MMC with HBSMs does not provide fault current blocking capability and a high current flows from the ac grid into the fault. This is a result of the freewheeling diodes' presence that provides an uncontrolled path for the dc fault to be fed by current from the ac grid through the upper and lower arms. This large current may damage the switching devices. The proposed qZS-MMC has an inherent dc-fault blocking capability feature. The fault blocking principle requires the injection of a negative voltage equal or higher than the peak value of the ac grid voltage in the path of the fault. In this converter, the qZS capacitors can be used to block the ac grid current during the fault by reversing their polarity connections as will be illustrated later.
Once the fault is detected, the switches of the MMC leg and the qZS networks are blocked. Then, a resonant current will flow through the qZS-inductors and capacitors, where the resonant path is highlighted in Fig. 9(a). This current makes the qZS-capacitor voltages V C1 and V C2 to be distributed equally, assuming they have the same capacitance. The initial qZS-capacitor voltages V 1 and V 2 are where C U 1 = C N1 = C 1 and C U 2 = C N2 = C 2 . V C1 (0) and V C2 (0) are the values of qZS-capacitor voltages at the initial instant of the fault. The positive polarity of the arm current i U A > 0 can be handled only by the diodes D 2 and D U . The SM capacitor voltages are connected in series with a summation equal to N S M * V C S M , which is larger than the peak value of the ac voltage. Therefore, the diodes D 2 and D U get a negative voltage at their terminals and then become open circuit. Furthermore, the negative polarity of the arm current i U A < 0 can be handled only by the diodes D 1 and D U 1 . Since the series voltage formed by qZS capacitors V C1 + V C2 is equal to or larger than the peak value of the ac voltage when using RICs' or SS techniques, respectively, with converter modulation index equals one, the diodes D 1 and D U 1 get a negative voltage at their terminals so these diodes become open circuit. Therefore, the ac grid current and the arm currents are quickly reduced to zero and the fault can be completely blocked. The blocking current paths for i U A > 0 and i U A < 0 are shown in Fig. 9(b) and (c), respectively.

VI. EXPERIMENTAL STUDIES
A reduced scale laboratory prototype has been built for the purpose of validating the behavior and performance of the proposed qZS-MMC. The schematic of the lab prototype is shown in Fig. 10. First, the operation principle described by the mathematical analysis has been verified using an RL load, which is illustrated by "load for Test 1" subcircuit in Fig. 10. The second test is to check the capability of the proposed converter to provide the dc-fault blocking capability using an ac grid, which is illustrated by "load for Test 2" subcircuit in Fig. 10. Table I summarizes the parameters of the components and Fig. 11 shows the actual hardware implementation of the prototype rig.
The control algorithm is implemented on a floating point 225-MHz TMS320C6713 DSP in charge of the calculations working in conjunction with an FPGA platform used for the A/D conversion of relevant voltage and current measurements and PWM signal generation. A daughter card is used for realtime data capture by a MATLAB host port interface (HPI). The experimental voltage and current waveforms are captured by a 200-MHz Lecroy oscilloscope, while the control state variables are recorded in MATLAB through the HPI. The DSP sampling and the PWM carrier switching frequency are both set to 10 kHz.

A. Test 1: Verifying the Analytical Model of the qZS-MMC Circuit
The first test demonstrates the necessity of using the antiparallel active switches in qZS networks (S U 1 and S N1 ). The dc-supply voltage used is 280 V, D sh was set to 0.15, and modulation index is set to 0.98 to avoid the harmonics caused by working in the proximity of the overmodulation region, which, according to (8), results in an expected peak value of the output voltage of 167 V. Fig. 12 shows the upper arm current i U A , the upper qZS-inductor currents i LU and i L S , and the upper dc-link voltage v U O . To prove that (22) is satisfied, the summation of the two inductor currents (i L S +i LU ) should be compared with the arm current i U A . Fig. 12 shows that the zero-crossing points of the channels Ch4 (i L S ) and Ch2 (i U A ) are the same and that the zero crossing of Ch3 (i LU ) is set at the average value of Ch4. It is, therefore, clear that when the waveforms of the arm current exceed the sum i L S + i LU , a negative current will be expected to flow through the diode which is impossible; therefore, the arm current has to remain equal to i L S + i LU , which will cause a drop in the dc-link voltage, as highlighted in Fig. 12(a). Fig. 12(b) shows that the arm current can be higher than i U A + i L S without a drop of the dc-link voltage as a result of using active switches in antiparallel with the series diodes to provide a controlled reverse conduction path.
The output voltage and current and their harmonic spectrums for the two cases are shown in Figs. 13 and 14, respectively. The scope data of the output voltage and current are extracted and used to display their FFT. The peak value of the fundamental output voltage as revealed by the FFT is 163 V. The difference between the expected peak value of the fundamental output voltage (167 V) and the actual  measured one (163 V) is caused by voltage drops on qZS inductors and the power semiconductor devices. Even though the converter delivers approximately the same fundamental voltage and current (in amplitude) in both the cases, using only the series diodes resulted in significantly higher level of loworder harmonics (third, fifth, and seventh). This distortion is also revealed by the differences in the total harmonic distortion (THD) values for the output voltage and current that are 19% and 8.5%, respectively, when using only the series diodes compared to 12% and 4.3%, respectively, when using also the antiparallel switches.
In another test, the performance of SS and RICs' techniques has been compared. The dc-source voltage was set to 225 V with converter modulation index of 0.98 and an ST duty ratio of 0.25 and 0.17 was used with the SS and RICs, respectively, to obtain the same voltage gain value (G = 1.48) with an  Fig. 16 for both techniques. It is noted that both cases have the same average capacitor voltage, which is 168.5 V despite different dc-link peak voltages. The peakto-peak capacitor voltage ripple in case of RICs' technique is 86% of that for the SS technique, which agrees with the design prediction in Fig. 6 at a gain value of 1.5. The upper and lower qZS-inductor currents and source current are shown in Fig. 17 for both modulation techniques. It is noted that the inductor currents i LU and i L N have a high ripple at fundamental frequency in case of using RICs' technique, where their peak equals twice of the average value, whereas the same currents are free from the low-order/fundamental frequency ripple when using the SS technique.
Since the stress voltage on the chain-link switches in the case of using the SS technique is high compared with the RICs' technique, and also applying only partial ST intervals of RICs as shown in Fig. 4 (i.e., half switching frequency), the qZS-network losses are higher when using the SS technique compared with the RICs' technique. Fig. 18 has been added which indicates the experimental efficiency curves of the    changing the load resistance value, while the output voltage is kept constant. The input power was measured by reading the voltage and current readings delivered by the power supply, while the output power was calculated by measuring the load current and then by knowing the load resistance, apply the I 2 R power relation. Using RICs' technique makes the converter has a higher efficiency compared with the SS technique.

B. Test 2: Operation Under DC Fault
To assess the response of the proposed qZS-MMC to a poleto-pole dc-side short-circuit fault, an ac supply has been added at the ac output terminals of the qZS-MMC. The dc fault has been implemented by using a contactor in series with a 2resistor to limit the fault current to a relevant level for such a test; this subcircuit has been inserted between points X and Y, as shown in Fig. 10. The dc supply voltage is set initially at 100 V and reduces quickly by 90% once the fault occurred due to the maximum current limitation of the dc voltage supply, as shown in Fig. 19(a).
The supply voltage, the grid voltage, the grid current, and the lower arm current are shown in Fig. 19(a). The controller detects the fault by monitoring the dc-side current (i Ls ) such that this current is reversed and rapidly increases exceeding an overcurrent threshold current level of −I L when the fault occurs. Once the fault is detected, all IGBTs are turned off. After the IGBTs are blocked, the grid current and the lower arm current fall directly to zero, as shown in Fig. 19(a). The inductor current i Ls oscillates following a natural resonance, as shown in Fig. 19(b), until it settles to zero which coincides with an absolute peak overshoot current of approximately 2.2 times the operating current from the steady-state condition. Although this value may be considered high, it should be noted that the resonant current only flows through the inductors and the capacitors of the qZS networks and this current does not flow through the chain-link switches S U , S N , S U 1 , and S N1 , as has been discussed in Section V. The chain-link switch current i SU is indicated in Fig. 19(b). The qZS capacitors C 1 and C 2 start to discharge and charge, respectively, until their voltages become approximately equal, as shown in Fig. 19(c) (Ch2 and Ch3 have the same zerocrossing position), whereas the SMs' capacitor voltages are kept mostly unchanged. To conclude, these results verify the dc-fault blocking capability of the proposed qZS-MMC.

VII. TOPOLOGIES COMPARISON
In Section VI, the attractive features of the proposed qZS-MMC have been showcased, which make it suitable for use in medium voltage/power wind turbines and/or photovoltaic generation systems. It is interesting to compare the proposed converter with the MMC based on FBSMs (FB-MMC) [25] and the quasi-Z-source cascaded multilevel inverter (qZS-CMI) [26], as they both are able to provide voltage boosting capability. The comparison has been carried out in terms of a number of passive and active components, conduction and switching power losses, and output voltage quality for the same output voltage level. The case study of a 6.6-kV, 5-MW wind turbine generation system as described in [25] has also been considered in this article.

A. Number of Components
The comparison here is carried out in terms of the required number of semiconductor devices, inductors, capacitors, and dc voltage sources for the same amplitude of output ac voltage in both single-phase and three-phase implementations. The peak value of output phase voltage was fixed to 5.4 kV, then the gain G is set to 2 to get the required source voltage, which is 5.4 kV. Regarding the proposed converter, considering four SMs per arm, each SM needs to have an average capacitor voltage equal to 2.7 kV. According to (9), and (19), the duty ratio needs to be set to 0. 25   IGBTs in FB-MMC as a reference, the total number of IGBTs required by r for the qZS-MMC with RICs' and SS techniques reduces to 75% and 87.5%, respectively, and to 62.5% for qZS-CMI in the case of a single-phase converter. For a threephase converter implementation, due to the fact that the qZS switches are shared with the other two phases, the number of IGBTs required by the qZS-MMC controlled by the SS technique decreases to 62.5%, which is considered a significant reduction in terms of number of semiconductor power devices, while it is 83% for qZS-CMI. It should be noted that a convenient three-phase implementation is not possible for the qZS-MMC with RIC. Table II summarizes the relevant steps in defining the power semiconductor requirements, inductors and capacitors, and dc voltage sources.

B. Losses' Comparison
To have a fair losses' comparison of the proposed converter with the FB-MMC [25] and qZS-CMI [26], it is mandatory to evaluate the losses using the same power semiconductor devices. To attain nine levels of the output voltage, four SMs per arm are required for both the proposed converter and the FB-MMC, while qZS-CMI requires four cascaded units per phase. Hence, 3.3-kV voltage rating IGBTs can be used, such as the 5SNA0800N330100 device to be used in the SMs and the chain-link switches. The estimation of the switching losses' model relies on the switching energies stated in the device datasheet, which are characterized by the manufacturer at an operating temperature of 125 • C which is then transferred in the generic PLECS thermal model. The FB-MMC is modulated using PD PWM (PD-PWM) [6], while the qZS-CMI can only be modulated using phase shift PWM (PS-PWM) technique [26]. The frequency of the triangular carrier signal f c is chosen to be 4 kHz for the qZS-MMC and FB-MMC, while the actual average number of commutations per second per SMs is shown in Table II. To make the comparison more credible, the PS-PWM technique used for qZS-CMI is adjusted to achieve the same number of transitions as that of  III   TOTAL SMS AND QZS-NETWORK CONDUCTION AND SWITCHING LOSSES PD-PWM by setting the carrier frequency to 1 kHz for the cascaded units in this case. It is worth to mention that the resulting shooting-through frequency is 2 kHz for qZS-CMI and 4 kHz for qZS-MMC. Table III shows the total conduction losses and switching losses in SMs and qZS networks and the total converter losses for each of the converter candidates and operating mode. As expected in the boost mode (at gains 1.25, 1.5, and 2), the RICs' technique adds more SMs' switching losses than the SS technique. This is a result of having to turn on/off N S M /2 of SMs during ST intervals that lead to an average switching frequency 3 f c /N S M , which is three times higher than in the case of using the SS technique ( f c /N S M ). However, the stress voltage on the chain-link switches is higher in the case of using the SS technique than the RICs' technique and by applying only partial ST intervals of RICs (see Fig. 4), the qZS-network losses are higher when using the SS technique especially with increasing the gain. Due to FBSMs having two switches in the current path rather than one in the HBSMs, the FB-MMC gets higher SMs' conduction losses than the qZS-MMC, which is up to three times more at higher voltage gain. In qZS-CMI, as a result of having to use the FB switches for implementing the ST, the qZS-CMI gets higher SMs conduction and switching losses.
In the buck mode, the qZS-MMC and qZS-CMI have lower total losses than the FB-MMC at gain equals to 0.7. In the boost mode, the FB-MMC has lower total losses (65%-70%) than the qZS-MMC with RICs, while the qZS-CMI and qZS-MMC that use the SS technique have approximately equal total losses. However, if the shooting-through frequency for the qZS-MMC is adjusted to be equal to the shooting-through frequency of qZS-CMI, the qZS-MMC will be more efficient than qZS-CMI. To conclude, the FB-MMC is more efficient than qZS-MMC with RICs in boost mode (especially when increasing the gain) where the total losses are 2.2% and 3.2% for FB-MMC and qZS-MMC with RICs at G equals 1.5, respectively. However, the qZS-MMC and qZS-CMI are more efficient in the buck mode with losses percentage equal to 2.4% and 2.2%, respectively, compared with 2.9% for FB-MMC at G = 0.7.

C. Comparison of PWM Harmonics Profile
The harmonic spectrum of the phase voltage of the FB-MMC, qZS-CMI, and qZS-MMC is compared and shown in Fig. 20 for different gains (1, 1.5 1.75, and 2). The SS and RICs' techniques produce the same harmonic profile; therefore, the harmonic profile has been shown for the RICs technique only. It is noted that the switching harmonics of the qZS-MMC with the two techniques appear as sideband clusters at the carrier frequency where the most dominant harmonic cluster is located at twice the carrier frequency (8 kHz) for all gain values. The harmonic profile of the FB-MMC at gain equals to 1 and 2 is similar to the qZS-MMC. However, at intermediary gain values, an additional dominant harmonic cluster appears for the FB-MMC at the carrier frequency. This is an important finding since a larger harmonic cluster at lower frequency will require an increased size for the filter. The switching harmonics of qZS-CMI appear as sideband cluster at twice the carrier frequency (8 kHz) for all gains. The THD of the output voltage of the qZS-MMC and FB-MMC is approximately equal to 9.2% and 8.7% for all gain values, respectively. For qZS-CMI, the THD equals to 15%, 18.2%, 23.3%, and 23.5% for the gain values of 1, 1.5, 1.75, and 2, respectively. This is because in order to increase the gain of qZS-CMI, the modulation index should decrease with increasing the ST duty ratio, which leads to a drop in the output voltage level, while the modulation index could remain fixed for all gains of the other converters.

VIII. CONCLUSION
A detailed mathematical model of the qZS-MMC has been derived for the two proposed modulation techniques. The operation of the proposed converter at the proposed two modulation techniques (SS and RICs) has been investigated and discussed. The capacitor voltage ripple in the qZS networks and the MMC SMs has been analyzed and compared for the two modulation techniques, which allows an estimation of the required capacitor energies and sizes. The ability of the proposed converter to block the dc-fault current has been investigated. A small-scale laboratory system has been built and has been used to demonstrate the performance of the proposed converter and its capability to handle the dc fault. Also, a comparison between the proposed converter, the MMC with FBSMs, and the qZS cascaded multilevel inverter has been carried out in terms of the number of the components, total conduction and switching losses, and output voltage quality. The number of IGBTs necessary to build the proposed qZS-MMC controlled by the SS technique is 62.5% and 75% of that required for MMC with FB and qZS-CMI, which is a significant reduction. In terms of semiconductor device losses, the qZS-MMC is more efficient in the buck mode. However, the MMC with FB is more efficient in the boost mode, especially with increasing the converter gain. Compared with the qZS-MMC, the MMC with FB has a significant harmonic cluster of the output voltage at the switching frequency, which will either require increasing the filter size or doubling the switching frequency. In the latter, the losses may increase to the point where the MMC becomes less efficient than the proposed qZS-MMC. The qZS-CMI has a high THD particularly with increasing the gain compared with the qZS-MMC and the MMC with FB.