A New Basic Unit for Symmetric and Asymmetric Cascaded Multilevel Inverters with Reduced Power Electronic Devices

In this paper, a new basic unit for the cascaded multilevel inverter is proposed. By series-connected numbers of the proposed basic unit, a new cascaded multilevel inverter is also proposed. In order to generate all (even and odd) voltage levels two new algorithms to determine the magnitude of dc voltage sources are proposed. Then, this inverter is compared with several conventional cascaded multilevel inverters that have been presented in the literature. Based on these comparisons, the proposed inverter is able to generate a higher number of output levels by using a lower number of power electronic devices, dc voltage sources and minimum variety of the value of dc voltage sources. As a result, high efficiency, reducing the size and cost of the inverter is the other advantages of the proposed inverter. Finally, the accuracy performance of the proposed cascaded inverter to generate all voltage levels is verified through experimental results on a 49-level inverter in a laboratory prototype.


INTRODUCTION
A multilevel inverter is a power electronic converter that generates desired ac output levels by using several dc voltage sources as inputs [1]. By increasing the number of dc voltage sources and semiconductor switches a sinusoidal-like waveform is generated at the output. Recently multilevel inverters have received more attention because of their capability in high power, high voltage applications. In addition, high power quality, reducing lower order harmonics, lower switching losses and better electromagnetic interference are other advantages of multilevel inverters [2], [3]. There are three main categories for multilevel inverters: Diode clamped multilevel inverter [4], flying capacitor multilevel inverter [5] and cascaded multilevel inverter [6]. The cascaded multilevel inverter is divided into two groups: symmetric cascaded multilevel inverter and asymmetric cascade multilevel inverter. In the symmetric state, the magnitudes of all dc voltage sources are the same while in the asymmetric state the magnitudes of dc voltage sources are different [7], [8]. In the cascaded multilevel inverter, there are any many diodes clamped and flying capacitor. In addition, reducing the stress on power switches and faulttolerant operations, extendibility, modularization, simplicity of control and reliability are some of the main advantages of these inverters in comparisons to two other multilevel inverters. However, a high number of required dc voltage sources and semiconductor power switches by increasing the number of generated output levels are disadvantageous of this inverter [9], [10]. The first cascaded multilevel inverter has been presented in [11]. This inverter is comprised of series connected of several H-bridges. In order to increase the number of output levels, different algorithms to determine the magnitudes of the dc voltage sources in the H-bridge have been presented in [11], [12]. Then, two other symmetric cascaded multilevel inverters have been presented in [13], [14]. The main problems of the symmetric cascaded inverters is a high number of required integrated gate bipolar transistors (IGBTs), dc voltage sources, power switches, and driver circuits by increasing the number of generated output levels because of its low magnitude of dc voltage sources. In [15][16][17], three other cascaded multilevel inverters have been presented. Three different algorithms to determine the magnitude of dc voltage sources as symmetric and asymmetric states have been presented for the presented inverter in [15]. In addition, two different algorithms have been considered for each of the presented inverters in [16] and [17]. Although all of other topologies have their own advantages in this paper, in order to increase the number of output levels by using a lower number of power electronic devices and dc voltage sources, a new basic unit is proposed. Then, by the series connection of the numbers of these basic units, a new cascaded multilevel inverter is introduced. In order to generate all positive and negative levels at the output two algorithms to determine the magnitude of dc voltage sources are proposed. The proposed inverter is compared with several conventional cascaded multilevel inverters to investigate its advantages and disadvantages. Finally, the accuracy performance of the proposed inverters is reconfirmed by using experimental results on a 49-level proposed inverter.

II. PROPOSED BASIC UNIT
The proposed basic unit is shown in Fig. 1. As shown in this figure, the unidirectional and bidirectional power switches are used in this topology. Each unidirectional power switch consists of an IGBT with an anti-parallel diode that is able to conduct current in both direction and block voltage in one polarity. While the bidirectional power switch includes two IGBTs with Two anti-parallel diodes that conduct current in both directions and blocks voltage in two positive and negative polarities. As a result, the unidirectional switch requires one driver circuit and bidirectional switch needs two driver circuits unless a common emitter structure is used. In this condition, each bidirectional power switch needs one driver circuit. In this topology, the power switches of 1 T , 2 T , 3 T , 1 S and m S are unidirectional switches while the power switches of 2 S , 3 S , , 2 m S  , 1 m S  and 3 T are bidirectional power switches. In addition, in order to generate the same steps output levels, the magnitudes of dc voltage sources have to be considered equally. In this topology, the power switches of 1 T is used to generate positive levels, the switch 2 T is used to generate negative levels and 3 T is used to generate zero levels. Table  I shows the switching pattern and generated output levels in the proposed basic unit. As it is obvious from this Table, the proposed topology is able to generate positive and negative voltage levels at the output. Moreover, in order to generate all voltage levels at the output except the zero levels, only two power switches in different operating modes are turned on. In order to simplify, the voltage drop of switch conduction state is eliminated.
In the proposed basic unit, the number of generated output levels () In the above equations m is the number of used power switches in the proposed basic unit without considering the constant power switches 1 T , 2 T , 3 T . One of the main parameters to determine the cost of the multilevel inverters is the value of power switches which is completely depended on the voltage and current of the power switch. Therefore, by reducing the current and voltage values of power switches the cost of the inverter is decreased [12]. Generally, in multilevel inverters, the current value of each power switch is determined by the load current value while the blocked voltage values of the power switches are different. As a result, the maximum blocked voltage value of power switches has the most important influence in the cost of the inverter. The value of this parameter is depending on the states of the switches. According to Fig. 1, the maximum value of the blocked voltage by unidirectional power switches 1 T , 2 T , 3 T are obtained as follow: The blocked voltage by unidirectional switches of 1 S and m S are the same and obtained as follows: The maximum blocked voltage by other bidirectional power switches are calculated as follows: Therefore, the blocked voltage by used power switches ( , block unit V ) in the proposed basic unit is obtained as follows:

III. SUGGESTED CASCADED MULTILEVELINVERTER
It is possible to series connected n numbers of the proposed basic unit to generate a new cascaded multilevel inverter. It is possible to develop the proposed inverter in both single and three phase system algorithms to determine the magnitude of dc voltage sources. So we propose two different methods to determine of dc sources magnitudes.

A. First Proposed Method
In the first proposed method, the magnitudes of all dc voltage sources are considered equally. In other word: The proposed inverter based on this method is known as symmetric cascaded multilevel inverter. In this condition, the number of generated output level is obtained as follows:

B. Second Proposed Method
In the second proposed method the magnitudes of dc voltage sources are considered as follows: First unit: Second unit: Third unit: th n unit:  In this section, the proposed cascaded multilevel inverter is compared with several cascaded multilevel inverters that have been presented in literature. This comparison is from the number of IGBTs, power switches, and dc voltage sources. In this comparison, the proposed cascaded multilevel inverter based on its algorithms are shown 1 P , 2 P . The H-bridge cascaded multilevel inverter with three symmetric and asymmetric algorithms that have been presented in [11], [12] are indicated 1 R , 2 R , 3 R , respectively. Two other symmetric cascaded multilevel inverters have been presented in [13], [14]. These inverters are presented 4 R , 5 R , respectively. In [15][16][17], the other cascaded multilevel inverters with symmetric and asymmetric algorithms have been presented. For the presented cascaded multilevel inverter in [15], there are three different algorithms as symmetric and asymmetric states. This inverter with its algorithms are considered 6 R , 7 R , 8 R , respectively In this comparison, the presented cascaded multilevel inverters in [16] are considered by 9 R and 10 R , respectively. The presented inverter in [17] by two different algorithms is indicated 11 R , 12 R , respectively. Fig. 3 indicates all of cascaded multilevel inverters topologies and Table II shows the presented methods that have been considered for this topologies.   Fig. 4(a) compares the number of IGBTs in the proposed topology with other cascaded multilevel inverters. As it is obvious from this figure, the proposed cascaded inverter needs lower number of IGBTs than other presented inverters in the references except for the presented inverter 12 R . This feature is remarkable when the second proposed algorithm is used. It is pointed out that the bidirectional and unidirectional power switches are used in the proposed cascaded inverter while in the most of topologies only unidirectional power switches are used. In addition, the unidirectional power switches are only used in the presented 12 R . The number of power switches in the proposed cascaded inverter is compared with other inverters. Fig. 3: The cascaded multilevel inverter structures in literature; (a) CHB; (b) presented in [13]; (c) presented in [14]; (d) presented topology in [15]; (e) presented in [16]; (f) presented in [17]. This comparison is shown in Fig. 4(b). As it is obvious from this figure, the proposed inverter needs lower number of power switches than other presented inverter in literature. As it is mentioned previously, all unidirectional and bidirectional power switches require a driver circuit. Therefore, the proposed inverter also needs lower number of power diodes than other inverters. Fig. 4(c) compares the number of dc voltage sources in the proposed topology with other cascaded multilevel inverters. It is clear that the proposed topology based on second proposed algorithm requires lower number of dc voltage sources than other mentioned topologies except the presented inverters 2 R , 12 R . This is because of the high magnitude of dc voltage sources in the presented inverter as 2 R , 12 R that lead to needs lower number of dc voltage sources to generate specific output levels. It is clear from the comparison; the proposed cascaded inverter is able to generate a higher number of output levels with a lower number of power switches, IGBTs and driver than other topologies. Although the proposed inverter requires a high number of dc voltage source than other topologies but this needs a lower number of power switches and driver circuits to generate specific output level. High number of required dc voltage source can be decreased by using renewable energy sources such as solar cell, wind etc.

V. EXPERIMENTAL VALIDATIONS
In this section, the ability of the proposed inverter to generate all voltage levels is reconfirmed by using experimental results on a 49-level inverter. This inverter is shown in Fig.  5. As it is obvious from this figure, this inverter consists of two basic units with ten unidirectional power switches, two bidirectional ones and eight dc voltage sources. It is important to note that the numbers of power switches in these two basic units are considered equally. In other word 12 3  mm . The magnitude of dc voltage sources are determined based on the second proposed algorithm. Based on (22) to (25) and considering 10 dc VV  , the magnitude of dc voltage sources in the first unit is equal to 1 10 VV  and in the second unit is 2 70 VV  . According to (26), this inverter has to be able to generate 49 levels with the maximum amplitude of 240V at the output. The IGBTs used on the prototype are HGTP10N40CID (with an internal anti-parallel diode) with the voltage and current ranges of 400 V and 10 A , respectively. The 89C52 microcontroller by ATMEL Company has been used to generate of switching patterns. In all process of the experimental performance the load is assumed as ). In this paper, the fundamental frequency control method is considered. The main aim of selecting the fundamental frequency control method is its low switching frequency that leads to low switching losses. In this experiment, the switching frequency is 50Hz . Figs. 6 show the experimental results. The output voltage waveforms of the first and second basic units are shown in Figs. 6(a) and 6(b), respectively. As shown in Fig. 6(a), the first unit is able to generate positive and negative voltage levels with the amplitudes of 0, 10V  , 20V  and 30V  . In addition, based on the Fig. 6(b), the second unit is able to generate seven levels with the magnitudes of 0, 70V  , 140V  and 210V  at the output. The output voltage of this inverter is obtained by adding the generated output levels of the first and second basic units that is shown in Fig. 6(c). According to this figure, the proposed inverter is able to generate 49 levels with the maximum magnitude of 240V at the output. The output current of the proposed topology with the maximum amplitude of 2.2A is also shown in Fig. 6(c). As mentioned before, the unidirectional and bidirectional power switches from voltage the point of view are used in this topology. As shown in Figs. 7(a) and 7(b) the blocked voltage by switches 1,1 S is positive and in switch 2,2 S is there is negative amount on voltage.

VI. CONCLUSION
In this paper, a new basic unit for cascaded multilevel inverters is proposed. By series connection of n number of this basic unit, a new cascaded multilevel inverter is proposed. Then, two different algorithms are proposed to determine the magnitude of dc voltage sources. This inverter requires a lower number of power switches, diodes, driver circuits, and dc voltage sources in comparison with conventional cascaded multilevel inverters that have been presented in the literature. Finally, all of the obtained theoretical issues are reconfirmed by using experimental results on a proposed 49-level inverter based on the second proposed algorithm.