An Unbalanced Capacitor Voltage Buck Converter With Wide Soft Switching Range

DC–DC converters using soft switching technology have gained popularity in several industrial applications. Nevertheless, a wider soft switching range and a simpler structure are the holy grail for these converters. In this article, an innovative unbalanced dc-link capacitor voltage buck converter with a broad soft switching range has been proposed. The converter uses an auxiliary switch and a small inductor to create an auxiliary network that enables zero voltage switching (ZVS) for the buck switch. The auxiliary switch turns on under zero current switching, whereas the main buck switch operates under ZVS with reduced dv/dt. Unbalanced voltage of a series-connected dc-link capacitor is intended to boost the soft switching range of the buck converter for a broad range of loads by lowering the resonant voltage to less than half the input voltage. LTspice simulations of the converter operating with a power load of 1 kW and a switching frequency of 100 kHz have been demonstrated and the efficiency of the topology based on silicon carbide MOSFET has been discussed. Compared with the traditional hard switching buck converter, the proposed converter reduces total losses by 50% and improves the light-load efficiency to 91.3% from 88.5% and the full-load efficiency to 97.5% from 94.5%. Finally, a 1 kW prototype has been designed and tested to validate the theoretical ideas including the closed-loop control strategy for the converter.


An Unbalanced Capacitor Voltage Buck Converter With Wide Soft Switching Range
Qinlong Chen , Christian Klumpner , Senior Member, IEEE, and Md Rishad Ahmed , Member, IEEE Abstract-DC-DC converters using soft switching technology have gained popularity in several industrial applications.Nevertheless, a wider soft switching range and a simpler structure are the holy grail for these converters.In this article, an innovative unbalanced dc-link capacitor voltage buck converter with a broad soft switching range has been proposed.The converter uses an auxiliary switch and a small inductor to create an auxiliary network that enables zero voltage switching (ZVS) for the buck switch.The auxiliary switch turns ON under zero current switching, whereas the main buck switch operates under ZVS with reduced dv/dt.Unbalanced voltage of a series-connected dc-link capacitor is intended to boost the soft switching range of the buck converter for a broad range of loads by lowering the resonant voltage to less than half the input voltage.LTspice simulations of the converter operating with a power load of 1 kW and a switching frequency of 100 kHz have been demonstrated and the efficiency of the topology based on silicon carbide MOSFET has been discussed.Compared with the traditional hard switching buck converter, the proposed converter reduces total losses by 50% and improves the light-load efficiency to 91.3% from 88.5% and the full-load efficiency to 97.5% from 94.5%.Finally, a 1 kW prototype has been designed and tested to validate the theoretical ideas including the closed-loop control strategy for the converter.

I. INTRODUCTION
B UCK converter is one of the most well-known dc-dc converters, which is frequently used to produce step-down dc voltage or schedule power flow.This type of converter has been found in widespread applications, including renewable energy storage systems, general industries, electric vehicles, and distributed generation systems [1], [2].Lightweight, small size, minimal losses, and high reliability are the desired characteristics for dc-dc buck converters.High switching frequency converter topology is a recommended candidate to improve the The authors are with the PEMC Group, University of Nottingham, NG7 2GT Nottingham, U.K. (e-mail: ezxqc1@nottingham.ac.uk; klumpner@ieee.org;ezzmra@exmail.nottingham.ac.uk).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TIE.2023.3314856.
Digital Object Identifier 10.1109/TIE.2023.3314856 power density due to the reduced size of passive components and smaller ripple currents [3].However, high switching frequency exhibits higher switching losses, and high dv/dt and di/dt result in excessive electromagnetic interference as well as switching OFF voltage spikes and switching ON current spikes [4], [5].
To alleviate these high switching frequency related restrictions, soft-switching techniques have been investigated in recent decades.Compared with the isolated converter for certain applications, the nonisolated soft switching topologies are more preferable owing to the disposal of the transformer and smaller structural dimensions [6], [7].The quasi-resonant tank converter (QRC), zero current state PWM (ZCS-PWM), zero voltage state PWM (ZVS-PWM), zero current transition (ZCT), and zero voltage transition (ZVT) are generic categories for non-isolated soft switching converter [8], [9], [10] (Fig. 1).However, despite having a wide load range and soft switching characteristics, the QRC converter devices have significant voltage stress and current stress and complex frequency control increases the size of passive components [11], [12], [13].The ZVS-PWM and ZCS-PWM converters use an auxiliary switch and a resonant inductor or capacitor to achieve soft switching [14], [15], [16], [17]; however, stress across the main switch voltage is high and hard switching occurs in conditions of light load.To accomplish soft switching, the ZCT and ZVT converters parallel additional auxiliary circuits [18], [19], [20], [21]; nevertheless, the auxiliary switch is hard switching, and more devices result in significant losses.
Utilizing an auxiliary loop that contributes to the soft switching operations, Yukinori proposed the snubber-assisted zero voltage and zero current transition (SAZZ) chopper [22], which has a simple control system and high efficiency.However, a duty ratio of greater than 50% restricts the soft switching range.In [23], a 2:1 pulse transformer is implemented to lower the resonant voltage to half the drain-source voltage of the main switch and extend the ZVS range to full duty ratio.However, this causes extra magnetic losses and requires high voltage stress on the auxiliary devices.Auxiliary resonant commutated pole (ARCP) is a popular topology for soft-switching inverters.Some papers proposed dc-dc converters based on the ARCP converter [24].Although this topology operates under soft switching, the charge balancing control for dc-link capacitors is complicated and tough to construct, especially when the system is dealing with a substantial amount of fluctuation in input voltage.
The unbalanced capacitor voltage (UCV) converter, which has a simple structure and control scheme, is initially suggested in [25] for a buck-boost converter.However, the buck-boost switch  is exposed to considerable current and voltage pressures and it creates an output voltage with reverse polarity.In this study, a brand-new UCV buck converter is proposed.It features two unbalanced voltage capacitors at the input dc link.The auxiliary loop comprises an additional switch and a resonant inductor (20% size of the primary inductor).This study addresses the novel use of the UCV approach to widen the soft switching range and perform soft-switching for a wide range of load conditions.Additionally, silicon carbide (SiC) MOSFETs are preferred for all switches due to their low ON-state losses, low parasitic capacitor, and fast switching speed that efficiently reduces losses of semiconductors in high-frequency converters [4], [26].
The rest of the article is organized as follows.Section II provides a full description of how the suggested topology works at steady state and at start-up conditions.The proposed topology has been proven to fulfill soft-switching operations with a variety of duty ratios and power loads in Section III.The simulation results using LTspice, a comparison of losses between the suggested soft-switching topology and the hard-switching buck converter, and the performance comparison between the proposed topology and other soft-switching topologies are shown in Section IV.The theoretical assumptions are validated by designing and building a 1 kW prototype, and Section V presents the experimental results.Finally, Section VI concludes the article.

II. TOPOLOGY DESCRIPTION AND OPERATION
The topology of the proposed UCV buck converter is presented in Fig. 2. Main switch S, freewheeling diode D, and inductor L m construct the basic buck converter.An additional switch S a and a small inductor L a consist of an auxiliary loop.The cs 1 and cs 2 are the parasitic capacitors acting as the snubber capacitors, which will resonate with the auxiliary inductor before the main switch S conducts in each switching period.To analyze the converter, it will be assumed that it functions in the steady state, as illustrated in Fig. 3.There are the gate source voltages for the main switch S, V gs and auxiliary switch S a , V gsa .I s and I d are the device currents of the main switch S and the freewheeling diode D, respectively.I Lm and I a are the inductor currents for L m and L a , respectively.V cs1 is the drain-source voltage of S and V cs2 is the diode (D) voltage.V c1 and V c2 are the voltages for input capacitors C 1 and C 2 , whereas V c1ss and V c2ss are the steady-state measurements.The converter's duty ratio is dr.As the period from t 1 to t 3 is only 2% of the switching period, the inductor currents at t 1 and t 3 as presented in (1) and ( 2) are approximately equal For the analysis, the following assumptions are taken into account.
2) V c1 and V c2 reach steady-state values V c1ss and V c2ss , respectively, at t 0 .3) All parasitic passive components of the gate drive circuits and power loop circuits are neglected, except the output capacitors of the main switch and the freewheeling diode, which are utilized for achieving soft switching turn-ON.

A. Analysis of the Work Modes in a Steady State
When this system operates in steady-state mode, the UCVs V c1 and V c2 attain their steady-state levels (V c1ss and V c2ss correspondingly).Each subperiod equivalent circuit is depicted in Fig. 4, which also provides explanations of the state steady operation's seven work modes.S and S a are switched OFF prior to t 0 when the power loop current freewheels through diode D for the first interval, and the specifications of each interval are detailed in the following.
Mode 1 [t 0 , t 1 ]: At the start of this subperiod, S a is turned ON under the ZCS condition.The main inductor current I Lm begins to flow into the auxiliary loop while I a increases linearly up to the minimal inductor current I Lm,min at t 1 .The current in the main diode I d falls steadily to zero, at which point the diode turns OFF under zero current state.This time of this interval is T 1 and there are no reverse recovery losses for this subperiod Mode 2 [t 1 , t 2 ]: This brief interval begins when the diode turns OFF under ZCS.The power loop current remains approximately constant (I Lm,min ).The output capacitors of S and D are charged and discharged using the auxiliary current.The auxiliary inductor L a and output capacitors cs 1 and cs 2 will be resonating.cs 1 's voltage is discharged to zero, whereas cs 2 's voltage is charged to V 1 .At the completion of the interval, the auxiliary loop current I a reaches approximately its maximum value (I a,max ).The time of this interval is T 2 .cs 1 's voltage and the auxiliary current I cs are calculated from ( 7) (5) where cs 1 ≈cs 2 ≈cs, ω is the natural frequency of the resonant circuit, and z is the characteristic impedance of the resonant circuit.
Mode 3a [t 2 , t 3 ]: The S drain-source voltage decreases to zero before the start of the gate signal.The resonant current I a flows through the antiparallel diode of switch S, whereas the loop current I Lm still flows through the auxiliary loop.ZVS conditions are provided due to the reverse direction of the switch current I s .
Mode 3b [t 3 , t 4 ]: At t 3 , the MOSFET is gated and due to the characteristics of MOSFET, when S starts to conduct under ZVS, the resonant current I a will flow through its channel and the antiparallel diode.The switch current (I s ) steadily rises from negative values to zero when the input current flows into the channel.Turn-ON losses are eliminated since switching current and voltage have no overlap.
Mode 4 [t 4 , t 5 ]: From t 0 to t 5 , the capacitor C 2 still discharges due to the auxiliary current direction.When S starts to conduct, the power loop current I Lm is transformed from the auxiliary loop to S, and the auxiliary current I a drops to zero with slope (V 1 -V c2 )/L a at t 5 .The time of this interval is defined as T 3 , which is half of the conduction period of S Mode 5 [t 5 , t 6 ]: When the auxiliary current I a falls to zero at t 5 , the power loop current begins flowing into the auxiliary Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.loop through the antiparallel diode of S a to charge C 2 and discharge C 1 concurrently.This is because the UCV V c2 is less than steady-state values V c2ss .Similar to mode 4, the auxiliary current reverses with the same gradient till it reaches -I a,max .After t 5 , S a can be turned-OFF at zero-voltage state.Because of the charge balance, the time interval is the same as mode 4 Mode 6 [t 6 , t 7 ]: When S turns OFF at t 6 , the power loop current begins to charge the capacitor cs 1 to input voltage V 1 and discharge cs 2 to zero.A large enough snubber capacitor will reduce the slope of drain-source voltage of S and reduce turn-OFF losses.T 5 is the brief time of this interval Mode 7 [t 7 , t 8 ]: After ZVS turn-OFF, the freewheeling diode operates.The power loop current flows through the diode.This interval is the same as the conventional buck converter.

B. Converter Start-Up Operation
When the converter starts, the voltage of point A is V 1 , whereas the voltage of point B is V 1 /2, as shown in Fig. 5. From the initial operation until steady state, the system is separated into N intervals (n = 1, 2, …, N-1, N, N+1, …).To simplify the startup analysis, the two distinct situations, without a control signal to the auxiliary switch and with the controlled auxiliary switch are considered.V c1 is initially equal to V c2 (V 1 /2).If the control signal of the auxiliary switch S a is removed, the antiparallel diode D sa replaces the auxiliary switch and there are three work modes (a), (b), and (c) as shown in Fig. 5. Fig. 5(d) and (e) shows the simplified circuits with the controlled gated auxiliary device.The two unbalanced capacitor currents are denoted as I c1 and I c2 , respectively.The ideal waveforms of removing control signals of S a are shown in Fig. 6.
Mode (a): Because the voltage at point B is less than V 1 , when the main switch S is turned ON, the input current I s will divide in two to flow into the auxiliary loop and load.Capacitor C 1  is discharged, whereas capacitor C 2 is charged.Peak-to-peak unbalanced capacitors current I c1 equals to I c2 , which is 50% of I a .The following equations correspond to Mode (a): Mode (b): This interval is initiated when S turns OFF and the freewheeling diode D starts to conduct.The current values of two capacitors I c1 and I c2 drop to zero with the same ramp value of V c2(n-1) /L a .The time of this interval is τ .
Mode (c): During this interval, the power loop current flows into load through the freewheeling diode D as the auxiliary loop current drops to zero.Before the input source reaches a steady state, the precharging happens and the dc-link capacitor current decreases gradually to zero, as shown in Fig. 7 V The values of I c1 and I c2 in this mode are The various voltage per cycle of V c1 differs from V c2 as depicted as ( 17)- (18).After Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.the steady state, the input voltage is constant and the input current I i decreases to zero ) where the dc-link capacitors C 1 and C 2 have the same capacitance C.
When the system enters an initial steady state, V c1 will be zero and V c2 will be V 1 .The system works as a conventional buck converter.Assuming the auxiliary control signals are presented after this steady state (V c2 = V 1 , V c1 = 0), two additional charge and discharge operations [mode (d) and mode (e)] are needed before restarting the cycle from mode (a).
Mode (d): The auxiliary switch S a turns ON prior to the main switch conduction.The power loop current is transformed into the auxiliary loop.The additional process happens when C 2 is discharged and C 1 is charged, simultaneously.This interval ends when I d reaches zero.
Mode (e): This subinterval occurs as the auxiliary inductor L a resonates with the output capacitor of S. When V cs1 becomes zero, the resonant current I a then flows into the antiparallel diode of S, which creates soft switching conditions.
The additional auxiliary switching modes make V c1 greater than zero.The steady state occurs when the auxiliary current area 1 is identical to area 2 because of the charge balance, as shown in Fig. 8.When V c1 is nearly zero or lower than half of V 1 , soft switching conditions are achieved for full duty ratios and full power loads in this topology.The steady-state ripple across capacitor voltage ΔV c,ripple is very small that can be determined by where T 1 , T 2 , and T 3 can be found from ( 4)-( 8).The steady-state dc-link capacitor voltages are shown in Fig. 9 and the rectangular boxes in the plot show the enlargement of the steady-state voltages.

A. Soft Switching Conditions
Soft switching operation is achieved when the snubber capacitor of switch S is discharged to zero prior to the switch conduction.According to (7), only when V c1 is less than V 1 /2, cs 1 can be discharged completely The minimum capacitor voltage V c2 can be determined from (7) by using the expression in (21).Using the derivative of ( 21) with respect to minimum power loop current I Lm,min , ( 22) can be derived by considering the main variable is the load power and other parameters L a , V 1 , z, and T 3 are fixed.So, only I Lm,min has an impact on the min/max values of V c2 .The sum of V c1 and The local minimum value is calculated from (22) as I Lm,min = T 3 V 1 /(2L a ).Substituting this value into (21), the calculated lowest V c2 /V 1 is determined to be 0.5 and the maximum V c2 /V 1 is close to 1. Modifying the various duty ratio and T 3 will have an impact on the minimum values of V c2 /V 1 .With the local minimum value of I Lm,min reinstated in (21), minimum V c2 /V 1 for various duty ratios are presented in Fig. 10.The results indicate that the resonant input voltage (V c1 ) is substantially less than half input voltage (V 1 ) for all duties.Therefore, the requirements for completely discharging cs 1 are presented.When duty ratio increases, the value of V c2 /V 1 rises steadily because of the reduced voltage difference between the output voltage and V c2 , which reduces the total increment of V c2 at start state.Since the UCV V c1 is less than half input voltage, soft switching for a full range of duty cycles is achievable.

B. Control Principle for the Proposed Topology
A straightforward control system similar to a conventional buck converter applies to the proposed converter.Gate signal for the main switch must be shifted by an advance time Te to be used as the gate signal for the auxiliary switch.The auxiliary switch conducts prior to the main switch, which provides ZCS conditions for diode.The auxiliary inductor resonates with snubber capacitor across the main switch, which yields the main switch ZVS turn-ON condition.During the resonance subperiod (mode 3b) before the switching current reverses direction, the main switch S needs to be turned ON, which determines the timing limit for the advance time Te (see Fig. 3).The time of t 2 -t 0 is expressed by T 1 +T 2 and the time of t 4 -t 0 can be calculated from (24).A look-up table for Te can be calculated offline and be used for the control of the converter.This simple control methodology for the auxiliary circuit avoids any potential stability issue for the converter

IV. SIMULATION VALIDATION AND COMPARISON
The proposed converter is simulated by LTspice utilizing SiC MOSFET SPICE models.Two SiC MOSFETs are used (C3M0016120K) as switches.The main filter inductor and output filter capacitor are selected using (25) and (26).The auxiliary inductor value is optimized based on the rms of auxiliary loop current (27) and preopen time T e as depicted in Fig. 11. 10 μH auxiliary loop inductor is selected to reduce the rms auxiliary loop current and shorten the preopen time, which ensures rms of auxiliary current I a is 4.69 A and the preopen time Te is 0.33 μs.The inductances of main inductor and auxiliary inductor are 875 and 10 μH, respectively.The parameters are calculated for a 500-240 V, 100 kHz buck converter with a rated power of 1 kW

A. Simulation Results
The startup and steady-state operations are validated by LTspice.The left plots of Fig. 12 show the system operating under the active control of the auxiliary MOSFET.V c1 is still reducing because area 1 and area 2 are not identical (see Fig. 8).When the system reaches a steady state (right plots in Fig. 12), V c1 and V c2 are approximately V c1ss and V c2ss , correspondingly, with the area 1 = area 2 .
The switching turn-ON and turn-OFF transient waveforms are illustrated in Fig. 13.The blue waveform is the main switch voltage V ds , the purple waveform is the switching current I d , the orange waveform is the diode current, and the green waveform is the auxiliary loop current I a .Auxiliary current is initially raised to I Lm along the orange dotted line as the diode current falls to zero without reverse recovery current.There is no overlap Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

LTspice results showing switching waveforms of the proposed topology (P
between the current I S and voltage V ds , which indicates zero turn-ON switching losses.Moreover, dv/dt of the main switch voltage V ds reduces 10 times compared with hard switching.The right plot in Fig. 13 depicts 42 μJ turn-OFF loss that is same as hard switching mode as no snubber capacitor has been used during the simulation.

B. Efficiency Comparison Between the Proposed Topology and Conversional Buck Converter
Based on the device datasheets, a comparative loss analysis has been presented between the proposed topology and the traditional hard-switching topology.Switch conduction losses, i.e., main switch conduction losses Ps cond and freewheeling diode conduction losses Pd cond and auxiliary switch conduction losses Psa cond have been considered.The switching losses include Ps on&off (main switch turn ON and turn OFF switching losses Ps), the diode switching losses Pd on&off , and the auxiliary switch switching losses Pa sw .The main inductor losses contain P Lm (the core losses P Lm,core and winding losses that include the high-frequency ac losses, P Lm,winding ) and the auxiliary inductor losses P La (the core losses P La,core and winding losses P La,winding ).Other losses include the driver losses (main switch drive losses Ps driver and the auxiliary switch driver losses Psa driver ), and the dc-link capacitor losses (P ci ).In comparison to the hard-switching buck converter, the proposed converter does not create switching losses Ps on and Pd on&reverse .Although Pa sw is zero, the auxiliary network produces additional conditional losses Psa cond and auxiliary inductor losses P La .The proposed soft-switching converter and hard-switching buck converter's total losses can be calculated using (28) and (29) P proposal = P cond + P s off + P Lm + P s drives + P ci + P La + P sa cond + P sa drives (28) The efficiency analysis is presented with a power load demand between 200 W and 1.2 kW (heavy load).Efficiency comparison

TABLE I PERFORMANCE COMPARISON OF THE PROPOSED TOPOLOGY AND PREVIOUS TOPOLOGIES
between the proposed topology and the hard-switching topology with the power levels from light load to heavy load is shown in Fig. 14.It is evident that although additional auxiliary circuit losses have been generated in the proposed topology, the switching losses of hard switching buck converter are far greater than the auxiliary circuit losses.In the proposed topology, the auxiliary losses are from 5.3% to 5.6% of total losses, and in hard-switching buck topology, the switching losses are from 26% to 57% of total losses, depending on the load power.For light load, the efficiency improves from 88.56% for hard switching to 91.3% for soft switching.The highest efficiency is maintained above 97.5% in the proposed topology at power levels up to 1.2 kW (heavy load), whereas the maximum efficiency is 94.6% for the hard switching converter.The efficiency of the proposed topology is around 3% greater than the efficiency of the hard-switching buck converter.Although additional components are needed for the proposed topology, if demand for the hard switching converter reaches the same peak efficiency of the proposed topology, a lower switching frequency needs to be selected, which will increase the size and weight of the converter.

C. Comparative Analysis With Other Soft-Switching Buck Converters
The proposed topology has been compared with other softswitching buck converters based on a performance matrix that includes the extra component quantity, additional voltage and current stress for devices, system controllability, soft switching range and efficiency, as shown in Table I.The quasi-resonant converter has been developed for decades [12], [13] because of its simple LC structures.The LC resonant processes occur before the switch turns ON or turns OFF, creates the ZVS or ZCS conditions for the main switch.However, complex frequency control is needed, which not only complicates the control but also makes it difficult to optimize the size of the inductor.The soft switching range is limited by switching frequency and duty ratio.The resonant inductor or capacitor is part of the power loop, which increases the switch current or voltage stresses.Moreover, hard switching will happen at light load, which reduces converter efficiency.A soft-switching PWM converter was proposed in [17].The main loop switch turns ON under ZCS and turns OFF under ZVS.But the topology needs additional six components, which increases the size and weight of the total system.Moreover, four power diodes are needed, which increases conduction loss.The main switch voltage stress increases by 200% and current stress increases by 133% compared with the conventional buck converter.
A zero-voltage transition soft switching topology was introduced in [19].An additional auxiliary loop similar to the proposed topology is used to assist soft switching operation.But the topology needs four extra components and the auxiliary circuit is part of the power loop.Therefore, the auxiliary inductor conducts current for the full switching period, which increases the size of the auxiliary inductor.The additional power diode generates additional conduction losses.Soft switching range is load dependent.Another family of ZCT converters was proposed in [21].The auxiliary loop is connected parallel to the power loop using coupling inductors.Due to the resonance process, the main switch sees additional voltage and current stresses.Timing calculation for the auxiliary switch increases control complexity and impairs dynamic response capability.
The SAZZ converter was proposed in [22].The auxiliary device conducts before the main switch.A simple control system is implemented, which increases the reliability and stability of the dynamic system.However, the auxiliary inductor is part of the power loop that will increase the auxiliary inductor rms current, and a large auxiliary inductor needs to be designed.Moreover, the soft switching operation only happens for duty ratio from 50% to 100%.In this work, the auxiliary loop consists of one semiconductor and a small-sized auxiliary inductor.The auxiliary loop works separately from the power loop, ensuring small rms currents for both auxiliary inductor and the MOSFET.This ensures the highest-rated efficiency among all six similar topologies.The simple control system provides a good dynamic response, which is suitable for high-switching frequency converters.The inherently UCV technique expends the soft switching operation under full duty ratios and full power loads, which is unique for a soft-switching buck converter.

A. Prototype Introduction
A 1 kW prototype of the UCV soft switching buck converter was built to validate the theoretical analysis and simulation results.SiC MOSFET and SiC Schottky diode are utilized as the main and auxiliary switches (SCTW100N120G2AG) and the freewheeling diode D (IDWD15G120C5XKSA1), respectively.Two 22 μF film capacitors were used as unbalanced voltage capacitors C 1 and C 2 .The 0.1 nF output capacitors of S and D were considered as cs 1 and cs 2 , respectively.The main inductor L m (875 μH) was designed with a ferrite core ETD 54.The auxiliary inductor L a needed a ferrite core ETD 34 and the measured inductance was 10 μH.For both magnetic components >60%, winding fill factor has been considered to reduce the size of the component.The closed-loop control had been implemented by a microcontroller board, launchxl-f28379d, which provides signals to the gate driver.The circuit parameters of the experimental prototype are presented in Table II.The soft switching operations of the proposed converter have been validated for both <50% and >50% duty ratios as well as the unbalanced capacitor operations using experiments.

B. Small Signal Modeling, Control Design, and Validation
To stabilize the output voltage in transient conditions, a closed-loop control scheme has been proposed in this section.Circuit parameters V c1 , V 2 , and I Lm are the state space variables Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
and the small-signal model is shown by (30)-(32) (30) For the proposed converter, source resistance R 1 = 0, and the small-signal model for the converter can be calculated as Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE II CIRCUIT PARAMETERS
The proposed control system utilizes the PI control for both current and voltage loops.The loop-gain Bode plots are shown in Fig. 15.In the low-frequency band, the magnitude of the gain is high and the gain decreases with -20 dB / decade, which eliminates the steady-state error.In the mid-frequency band, the zero-crossing point ωc is 1 kHz, and the phase margin is 43°, with the gain decreasing at a slope of -20 dB/decade, which ensures a fast response and good stability.The dynamic test results for power load changing from 800 to 400 W are shown in Fig. 16, where the purple line is the output current and the green line is the output voltage (experimental).The response time is only 0.4 ms and the output voltage remains stable at 200 V.

C. Experimental Validation
The experimental prototype rated at 1 kW and 100 kHz switching frequency was tested for duty ratios both above and below 50%.Figs.17(a) and 18(a) illustrate the main current waveforms for dr>0.5 and dr<0.5, respectively.When current starts in the auxiliary loop, the diode current drops to zero.Then, the resonant process starts and the switch current starts flowing through the antiparallel diode until the output capacitor is discharged completely, which matches with the theory and simulation.However, the parasitic capacitors and inductors in the circuit cause additional high-frequency ringing when the auxiliary switch turns ON.The main switch experiences soft switching as depicted in Figs.17(b) and 18(b) for dr>0.5 and dr<0.5, respectively.The main switch S turns ON under ZVS for both duty ratios.
The UCVs are shown in Figs.17(c) and 18(c).V c1 is 21 V for the duty ratio of 0.48 and 20 V for the duty ratio of 0.54, which are both less than half of the input voltage.Therefore, the main switch output capacitor cs 1 can be discharged fully during the resonance subperiods.With the increase of duty ratio, V c2 decreases, which validates the theoretical startup analysis (see Section II-B).The switching waveforms of the auxiliary switch and the freewheeling diode are depicted in Figs.19 and 20, respectively.The auxiliary switch turns ON under ZCS and switches OFF under ZVS (no overlapped area between voltage and current during switching transients).The voltage and the current stress of the auxiliary switch are tested during experiments.The rms auxiliary current is almost 40% less than the power loop current at full load and the auxiliary device voltage stress is the same as the unbalanced capacitor C 2 voltage.The negative area of the I d (see Fig. 20) is not the reverse recovery current, it is the parasitic capacitor, cs 2 , charging current when the diode turns OFF, which depicts there is no switching loss during the diode turn OFF.Therefore, the diode turns ON under ZVS and turns OFF under ZCS.The input and output voltage ripples are less than 1%, which is evident from Figs. 17(c) and 18(c).This proves soft switching does not affect the voltage or current ripples at both input and output of the converter.

VI. CONCLUSION
This article presented a novel use of the unbalanced dc-link capacitor, which enables soft-switching conditions in a buck converter for all switches and full-duty cycle and load ranges.A simple auxiliary structure was proposed that contains one additional MOSFET and one small-size auxiliary inductor that is 80% smaller than the main filter inductor.The steady-state working principle of the topology had been investigated.By controlling the auxiliary switch, the input voltage is distributed unequally between two dc-link capacitors, which creates suitable soft switching conditions for the main switch.Compared with the hard switching buck converter, the proposed topology avoids the reverse recovery losses of the freewheeling diode and switching losses of the main switch, which enables 100 kHz switching frequency for the converter.Simulation and experimental results based on a 1 kW SiC prototype validated the theoretical analysis of soft switching.An efficiency comparison between the proposed topology and the hard switching buck converter showed that losses in the auxiliary loop are still lower than the switching losses thus granting 50% reduction in total losses for both light load and full load conditions.The improved efficiency will be beneficial to minimize the size of the heatsink, increase the power density, and advance the switching range for future high-performance dc-dc converters.

Manuscript received 10
May 2023; revised 5 August 2023; accepted 1 September 2023.Date of publication 5 October 2023; date of current version 13 April 2024.This work was supported by the University of Nottingham Faculty of Engineering under FPVC Grant.(Corresponding author: Qinlong Chen.)

Fig. 6 .
Fig. 6.Ideal waveforms of the start-up without control signals of S a .

Fig. 7 .
Fig. 7. Ideal current waveform of mode before steady state.

Fig. 8 .
Fig. 8. Ideal waveforms of the startup with control signals of S a .

Fig. 11 .
Fig. 11.Calculated the rms auxiliary loop current values and per-open time with different auxiliary inductance.

Fig. 12 .
Fig. 12. LTspice results showing start state and steady state of the proposed topology (P in = 1 kW).

Fig. 14 .
Fig. 14.Efficiency comparison between the proposed topology and hard-switching buck topology (power from 200 W to 1.2 kW).

Fig. 16 .
Fig. 16.Dynamic response of the converter (experiment) with a step change of power from 800 to 400 W.