New Asymmetric Cascaded Multi-level Converter with Reduced Components

Multi-level converters have been used in several industrial applications. The following work seeks to present a novel power inverter structure featuring a low amount of devices for a multi-level converter with an asymmetric cascaded connection. The suggested architecture consists of a modified T-type structure and a half-bridge inverter that is back-to-back connected. The proposed circuit includes five dc voltage sources and nine semiconductor switches that generate 23 levels. To show the superiority of the proposed structure, a detailed comparison is made with other comparable multi-level converter structures. Simulations in MATLAB/Simulink are shown to validate the behaviour of the proposal.


I. INTRODUCTION
Multi-level inverters (MLI) are the main selected power conversion devices in industrial applications. These applications mostly comprise motor drives for all voltage and power ratings. Multi-level inverters are also finding their applications in grid-connected systems, uninterruptible power supply (UPS), electric vehicles and FACTS devices. All these applications are possible due to the ability of the MLI to provide a better output voltage with a more sinusoidal shaped waveform, improved efficiency due to lower switching frequency operation of switches, lower blocking voltage requirement with reduced dv/dt and improved electromagnetic compatibility. Another positive impact of MLI is the reduction of the filter size and cost due to reduced harmonics at the output [1]- [7]. The conventional multi-level inverter structures with the industrial application include flying capacitor (FC), cascade H-bridge (CHB) multi-level and neutral point clamped (NPC) inverters [8]- [11]. Cascaded H-bridges inverter makes for modularized design and package. In CHB, the output levels count may be double than the count of dc sources. CHB can be classified into two groups: asymmetrical and symmetrical structures, which are given by the dc source magnitudes. For a symmetric architecture, the magnitude is the same for the different dc voltage sources. For an asymmetrical architecture, the dc sources magnitudes are selected differently to reach maximum output voltage level [12], [13].
Several new structures for MLIs and their control are developed in [14], [15]. The main driving force for the design of new multilevel inverter structures is the reduction of the components count and total standing voltage (TSV) of the structures [16]- [18].
This research proposes a new module MLI which reduces the components count compared to other MLI structures. The total standing voltage is also reduced in this structure. Next, a new cascaded MLI is introduced by choosing the magnitude of dc sources differently. The capability of the proposed structure is demonstrated by a comparison between the new architecture and other MLIs, including aspects such as quantity of devices, dc sources and the amount of TSV on switches.

A. Proposed New Module
This paper seeks to introduced the general basic architecture of a 23 voltage-level optimal inverter which is depicted in Fig. 1. The module has five dc sources along with nine unidirectional switching devices S 1 ,S 1 , S 2 ,S 2 , T 1 ,T 1 , T 2 ,T 2 and one bidirectional switch S 3 . Dc sources values are wich are all different. Therefore, the proposed structure offers an asymmetric structure. This module uses a two-switch configurations: unidirectional and bidirectional. To avert short-circuits in the dc sources, the unidirectional switches S 1 ,S 1 , S 2 ,S 2 , S 3 , T 1 ,T 1 , T 2 ,T 2 operate in an opposite mode. In this basic module, switches T 1 ,T 1 are used to generate positive levels and switches T 2 ,T 2 are used for negative levels. Considering this information, Table  I details the feasible switching combinations of the suggested module. The optimal module creates nine levels by choosing the values of dc sources equally. If these magnitudes are different, the suggested inverter will generate more voltage levels. In this paper, they are considered as follows: The TSV of the switching devices of this inverter is: The blocking voltage of the pair of switches is equal to: Thus, TSV by the power switch can be written as follows: After calculation, the amount of TSV on each switch is obtained as: Considering the above relations and (9), T SV is defined as:

B. Proposed Cascaded Connection
Cascading several modules is another way to grow the level counts ( Fig. 2). In order to maintain the modularity, each module connected in cascade is assumed to be identical, i.e. the number of components is constant. This will generate more levels count from the cascade connection with a constant number of devices. The equations of components and T SV for the proposed configuration with n modules are detailed in Table II.

III. COMPARISONS STUDIES
In this section a comparative study considering three cascaded MLIs detailed in [8], [11], [16], is presented. This analysis is done to show the capability of the suggested structure. Table II gives the comparison of the different basic modules of the proposed structure, considering the quantity of components, dc sources and TSV against the quantity of levels in operation mode II and mode III. Various amounts of dc sources are chosen within the presented structures [8], [11], [16]. Thus, in all the structures the best modes of operations are selected which can create a maximum number of levels with the fewer devices count. For the selected structures [8], [11] and [16] two operation modes are considered for a better comparison according to Table IV. The variation of switches count against the levels count in all presented structures and the proposed structure are all modes indicated in Fig. 3(a). It can be seen that the proposed cascaded MLI produces the same voltage levels count with less switch counts compared to other cascaded MLIs. For example, the proposed structure for the generating 31 voltage levels in the proposed mode III required nine switches and [16] in mode II, twenty-two switches and other structures need up to  twelve switches. In the proposed structure, the driver's count is same as the switches count; so another benefit of the proposed structure is the reduction of the drivers count.
The variation of IGBTs count against the levels count among proposed cascaded MLI and other cascaded MLIs are displayed in Fig. 3(b). The proposed structure produces same levels count with less IGBT count compared to other MLI structures. Similarly, the proposed structure for generating 31 voltage-levels based on mode III requires ten IGBTs, which are lesser amount of IGBTs required compared to mode II in [16], which require twenty-three IGBTs and other structures need up to twelve IGBTs.
Reducing the number of dc voltage sources has been another important criterion in selecting an MLI. Fig. 3(c) indicates the variation between the dc voltage sources count required among the proposed structure and other MLI structures in all modes. According to Fig. 3(c), the proposed structure create same number of levels with lower dc voltage sources in mode II compared to [11], [16] in mode I, except for the CHB and [16] in mode II. Fig. 3(d) displayed the variation between N varity and levels count in the proposed cascaded MLI and other cascaded MLIs. As can be seen from Fig. 3(d), the cascaded MLI in mode II, creates the same amount of level counts with lower N varity compared to other MLI structures.
The variation in TSV compared to the levels count among the proposed MLI structures are indicated Fig. 3(e). The TSV's values are different in classical CHB and for present structure and MLI structures presented [16] are the same in both of the proposed modes.
According to Fig. 3(d), the proposed cascaded structure is decreasing the value of TSV compared to other MLI structures, except CHB. The CHB must be supplied differently with a higher rate of switches because the rate of voltage on switches is higher in each unit than in the proposed structure. Also, it is clear that CHB structures require many switches, IGBT, and drivers in comparison with the proposed cascaded structure.
Generally, the application of autonomous dc voltage amounts is not possible within MLI structures and the suggested structure. There are two options for solving this issue, the first option applies the multistep transformer that can set a desired input voltage by modifying the secondary turns of the transformer [17]. The second option is employing dc-dc converters that can generate the desired input voltage [18].
Therefore the proposed cascaded structure reduces the components count based on this comparison using the same levels count than other cascaded MLIs.
Negative Level With H-bridge With H-bridge Inherent Inherent

IV. SIMULATION RESULTS
In order to test the cascaded MLI, a single-phase 45-level cascade structure using mode II is simulated under MAT-LAB/Simulink software. Fig 4. indicates the power structure of the single-phase 45-level proposed cascaded structure that comprised two basic modules. The whole of semiconductor devices such as switches and diodes are supposed ideal in this simulation. Here, the selected values of input dc voltage sources are established on mode II i.e. V 1,1 = V 2,1 = V 1,2 = V 2,2 = 50V , V 3,1 = V 3,2 = 150V , and V 4,1 = V 5,2 = 300V . The peak of the output voltage is 1100V having a voltage step of 50V with 50Hz output frequency. For this simulation, the kind of load is a series connected R-L load with amounts of 150Ω and 10mH.
Fundamental frequency commutation, space vector (SVPWM) and pulse-width modulation (PWM) techniques are conventional control strategies for the switching of MLI structures [19]. In the proposed cascaded MLI for production of the gate pulse of switches, the fundamental frequency control switching is applied because this strategy works with the fundamental frequency. Namely, this strategy turns on and turns off switches only one time in each switching period, which reduces the switching losses compared to other switching strategies [20].
The     positive and negative voltages. The 45-levels of the suggested cascaded MLI is illustrated in Fig. 5(c) which is very close to a sinusoidal curve. The voltage's peak of the cascaded connection is 1100V with a voltage step of 50V . Fig. 5(d) illustrates the current output curve of two cascaded modules that peak of current is 7.3A. FFT values for the output current and voltage are shown in Figs. 6(a) and (b). From this figure, it is evident that the value of FFT for the load voltage is 0.03% and for the output current is 0.86%. The simulation results of suggested cascaded inverters reconfirm the proposal of new suggested topology based on theoretical design. The suggested cascaded inverter generates a sinusoidal waveform at the output with low harmonics without LC output filters that it can account a superior advantage of the suggested structure.

V. CONCLUSION
A new 23-level optimal inverter structure has been introduced in this paper with the advantage of having reduced switching device and dc voltage sources as well as blocking voltage. To achieve all levels, two different modes of dc voltage selection have also been presented. Both of these modes reduce the need for switching devices count and blocking voltage, which makes the proposed structure more practical. An in-depth comparison with other recently presented structures demonstrates the benefit of the presented asymmetric structure. The theoretical explanation of the suggested structure was verified by simulations.