An Interleaved Soft Switched High Step-Up Boost Converter with High Power Density for Renewable Energy Applications

— In this paper a novel soft switched interleaved boost structure with a simple auxiliary circuit is proposed which is suitable for stand-alone loads or AC grid applications. In this topology, coupled inductors and switched capacitor cells of parallel modules are merged to obtain high voltage conversion ratio. The converter also has the capability of adding extra switched capacitor cells to attain very high voltage gain. In order to provide soft switching condition in the wide range of output power, a new ZVT auxiliary circuit is employed which is responsible for soft switching of both phases and benefits from low conduction losses, the minimum number of semiconductor elements and only one auxiliary gate driver. These merits provide very high efficiency at both full load and light loads. More importantly, no auxiliary magnetic components are utilized by taking advantage of the leakage inductance of coupled inductors for the resonant network. All semiconductor components operate under soft switching alleviating the reverse recovery problem and switching losses. Besides, the converter benefits from common ground between input and output which simplify voltage feedback. The experimental results of the converter prototype with 400 V output voltage at 400 W are provided, which verify the advantages of the proposed approach.


I. INTRODUCTION
In the present day, due to the deficiency of fossil fuels and serious environmental problems like global warming and air pollution, clean and eco-friendly energy sources such as fuel cells (FC) and photovoltaic (PV) systems have considerably experienced meteoric growth [1], [33].One of the conspicuous applications of these sources is high voltage stand-alone loads (400-800V) or AC grid applications which require high DC voltage at the input stage.Hence, using such renewable energy sources which have generally a low generated DC voltage (usually 12-72V), demands high step-up and high-efficiency DC-DC converters [1], [42].
The classical boost converter is considered as the first solution to lift the output voltage.However, this converter suffers from low voltage gain and high voltage stress across the switch in such a way that to supply high voltage loads an extreme duty cycle is required.This results in high losses and low efficiency.To address the mentioned limitations, diverse structures have been presented so far [2].Utilizing coupled inductors, voltage multiplier cells, and switched capacitor techniques in the boost structures are well-known solutions to obtain high voltage gain [3]- [6].In [7], coupled inductor technique has been presented in which high voltage gain is obtained by adjusting the turn ratio of the coupled inductor.The main issue of using coupled inductor is making voltage spike across the switch due to the leakage inductance.To suppress spike voltage of leakage inductance, clamp and passive structures are applied [8].Utilizing switched capacitor technique [3], voltage multiplier cell [4], and the combination of them [5] are other general approaches to extend voltage gain.In the converter presented in [9], the switched-capacitor technique is used to achieve high voltage gain.One of the shortcomings of the introduced converter is that the power switch suffers from relatively high voltage stress, though improved voltage gain is achieved.
Using parallel DC-DC structures to increase and attain the desired power level is a common approach for medium and high-power applications.Parallel step-up structures benefit from the plethora of merits including the realization of thermal distribution, increasing power level, reducing current stress of diodes, and size reduction of semiconductor elements.Among parallel structures, interleaved ones can provide lower input ripple current which is an outstanding feature to reduce the size of the input filter and cost reduction.On the other hand, the same as the traditional boost converter, the conventional interleaved boost structure has low voltage gain [8].To solve this problem, the abovementioned voltage-boosting techniques are combined with the classical interleaved boost converter, and a high voltage gain is obtained [10].In [11] and [12], coupled inductor and switched capacitor cells are employed in the interleaved structure and high voltage gain is achieved without utilizing a large duty cycle.Also, in these converters, leakage energy is absorbed and spike voltage across the switches is suppressed by using the passive clamp technique.Nonetheless, semiconductors in these converters operate under  hard switching conditions, and many passive elements are utilized resulting in excess cost and low efficiency.
The necessity of employing converters with the high-power density and high efficiency in today's power electronics applications requires using soft switching techniques to be able to augment the switching frequency and improve the efficiency of the converters [13].Various soft-switching methods such as lossless snubbers, active clamp, and ZVT techniques have been presented by far [14]- [25].The lossless passive snubber is a general technique to provide soft switching performance in which no extra auxiliary switch is utilized.These structures suffer from high number of passive elements resulting in high EMI and conduction losses.Also, in the lossless snubber techniques, due to providing zero-current turn-on condition (ZCS) and having capacitive turn-on loss (  ), the efficiency is adversely affected, and the switching frequency is confined [14], [15].Another effective soft-switching technique is the active clamp, which employs low number of components containing an extra switch and a capacitor which contributes to high efficiency and power density [16][17][18][19][20].The main issue with this technique is losing soft switching performance at light loads, inasmuch as discharging the snubber capacitor and proving soft switching condition at turn on instances is dependent of output current and the stored energy in the leakage inductance [13].In, [20], an active clamp interleaved step-up converter is proposed.To provide soft switching condition in a wide range of output power, a very large leakage inductance is required to use.This results in the lost duty cycle and extra losses, degrading the voltage gain of this converter.Unlike active clamp circuits, the zero-voltage transition (ZVT) technique can provide soft-switching conditions in a wide range of output power and input voltage independent of output load.In [26]- [31], different ZVT cells composed of additional semiconductors, windings, and cores is employed for the boost converter to achieve soft switching condition which have a complex structure and requires high cost.
Using soft switching techniques in the interleaved step-up structures is also vital especially for medium and high power high-frequency applications, but it has some challenges.As the interleaved converters inherently have a more complex topology than single module structures, providing softswitching conditions with a simple structure, the low number of auxiliary components and low cost is of great emphasis.Also, in the high step-up applications used for solar inverters, employing a soft switched method that can operate in a wide range of output power and the input voltage is a key factor [32].Therefore, ZVT cells can be a proper candidate for soft switching of such applications because of providing the softswitching condition independent of output load.In [21], a ZVT cell for a high step-up interleaved converter is proposed.Although this cell can provide soft switching in a wide range, it is made up of many auxiliary components including two extra switches, two magnetic elements, and two diodes which dramatically increase the conduction losses and have a low power density.Furthermore, not only the voltage gain of this converter is relatively low, but also having no coupled inductors, the voltage gain cannot be further increased.In [5], a ZVT cell utilizing coupled inductors has been proposed in the Z-source converter to improve soft switching condition at turn off instances of the switches.This ZVT structure is also employed for the interleaved topology, which involves one auxiliary switch, two diodes, and two extra windings [30].Also, this topology does not have high voltage gain, and suffers from high conduction losses.In [22], an interleaved ZVT converter with high voltage gain and low switch voltage stress is introduced.Using two extra winding and three semiconductor components is the noticeable disadvantage of this converter.Additionally, the mentioned converter cannot operate with duty cycles lower than 0.5, which is a weakness for a high step-up converter; in practice regulating the output voltage from no load to full load condition is essential.In [25], an interleaved ZVT high step-up converter based on coupled inductors and switched capacitors is introduced.The ZVT cell in this converter is composed of four extra diodes, one switch, and two windings which has reduced the power density and suffer from high cost and conduction losses.Moreover, despite of using high number of components, it possesses a proportionally low voltage gain, and its output diode has a very high voltage stress.In [24], a ZVT boost converter is proposed using switched capacitor technique as a multiplier cell.The introduced ZVT cell in this converter has lower number of components than the abovementioned ones, but the voltage gain of this step-up converter is not so high, it is a bit higher than the conventional boost converter.In [23], another ZVT interleaved converter with a very high voltage gain and efficiency is introduced utilizing two separate auxiliary circuits for soft switching of main switches.Not having any shared ZVT elements results in high number of components.
In this paper, a new ZVT interleaved converter is proposed based on coupled inductors and switched capacitor circuits, providing high voltage gain and low voltage stress across main switches.The proposed ZVT cell employed in this structure is compatible with high step-up coupled inductor-based boost converters.By making use of the leakage inductance in the resonant network, no extra magnetic elements are needed and only one bidirectional switch and one resonant capacitor are utilized for the ZVT structure.Note that the structure of the proposed auxiliary circuit is very similar to active clamp auxiliary circuits, but the operation is completely different.Unlike the active clamp circuit, the capacitor in this cell provides a resonant network and the soft switching is load independent.Also, only one auxiliary circuit is used for two phases of the interleaved structure.The proposed converter possesses the minimum number of components and has the capability to add extra multiplier cells to achieve very high voltage gains.In the proposed converters, soft switching operation of the main and the auxiliary MOSFETs are achieved independent of the line and load which results in a high efficiency in the wide range of output power.Having common ground between input and output and no reverse recovery problem are other advantages of the proposed ZVT converters.
The proposed converters are presented and analyzed in Section II and its operating modes are discussed.Design considerations are introduced in Section III.Finally, Section V provides experimental results and comparisons.

II. OPERATING PRINCIPLES
The proposed ZVT interleaved converter is shown in Fig. 2(a).As the proposed ZVT cell employs the leakage inductance of coupled inductors, only one capacitor and one bidirectional switch are needed in the auxiliary cell.Adding extra multiplier cells can increase the voltage gain of the proposed converter, like the second proposed converter which is shown in Fig. 2(b).Due to the similar operation of the first and second converters, the first proposed one is selected to investigate.In order to consider operating modes of the proposed converter, the equivalent circuit is presented in Fig. 3.This converter is composed of two coupled-inductors  1 ,  2 and  3 ,  4 with, respectively,  1 ,  2 ,  3 , and  4 winding turns ( and the power switches  1 and  2 , capacitors  1 ,   , and   , and diodes  1 ,   , and   .Also, the auxiliary circuit is composed of   capacitor and a bidirectional switch   , which is implemented with two unidirectional switches  1 and  2 .In order to simplify the analysis, diodes and switches are assumed ideal, the voltage of capacitors  1 ,   , and   and the magnetizing inductances  1 and  2 are supposed to have low current ripple so that they are considered constant and  1 ,   , and   are equal to Mode 1 [t0-t1] (see Fig. 4a): At the beginning of this mode, the main switch  1 is turned off under ZVS condition due to the existence of the snubber capacitor,  1 .During this mode, all switches and diodes are off excluding switch  2 .In addition, CS1 capacitor is linearly charged via magnetizing inductance current (ILm2) and the load is supplied by the output capacitor.Below equation is true for the voltage of the snubber capacitor.At the end of this mode, the voltage of snubber capacitor,  1 reaches , in which D is the duty cycle of main switches.Therefore, the time duration of this mode is as follows: Mode 2 [t1-t2] (see Fig. 4b (3) Where  1 and   are equal to   /(1 − ) and 2  /(1 − ).
Mode 3 [t2-t3] (see Fig. 4c): At the commence of this mode, the auxiliary switch   turns on under ZCS condition due to the existence of  2 ;  1 and the anti-parallel diode of  2 starts to conduct.In this mode,  1 is equal to   and is considered almost constant, but ILk2 starts to increase linearly.Thus,   and   decrease.When ILk2 reaches   current,   becomes zero and   turns off under ZCS condition.Due to the short duration of this mode, its time interval can be neglected.
Mode 4 [t3-t4] (see Fig. 4d): Once Do turns off at  3 , a constant voltage is placed across leakage inductances and   starts to decrease linearly.At the end of this mode  2 reaches  1  and   becomes zero.So,   turns off under ZCS condition at t4.The equations of this mode are as follows.The time duration of this mode is short and can be neglected.
where   =  2 +  1 Mode 5 [t4-t5] (see Fig. 4e): By turning   off at  4 , a resonant network is formed between   ,  1 ,  2 , and  1 .During this resonance,  1 increases and  1 and   decreases.By the end of this mode,  1 reaches zero and body diode of switch  1 conducts. Where and  1 = In this mode, the resonance continues between   ,  2 and  1 and the leakage inductance current decreases in a resonant manner.Also, due to conduction of  1 , the main switch,  1 can be turned on under ZVS condition at any time during this mode.In this interval, the voltage of   capacitor decreases to zero, then charges in a negative direction and at the end of this mode,   is clamped to −(  −   ) voltage, which is approximately equal to . Also, at  6 ,  1 and  2 decreases to zero, and the body diode of  1 turns off under ZCS conditions.Thereafter, the auxiliary switches can be turned off under ZCS condition. ) Where Mode 7 [t6-t7] (see Fig. 4g): In this interval, both main switches are on and the input voltage is applied across  1 and  2 so that their currents are increased.The time duration of this mode is equal to Mode 8 [t7-t8] (see Fig. 4h): At the beginning of this mode, the main switch,  2 , turns off under ZVS condition due to the snubber capacitor  2 .So,  2 is linearly charged by the magnetizing inductance current  2 .At the end of this mode,  2 reaches ,   remains off and  1 starts to conduct.In this mode  2 passes through  1 ,  1 and  1 switch and  1 is charged.The equivalent circuit in this mode is shown in Fig.
Mode 10 [t9-t10] (see Fig. 4g): At  9 ,  2 is turned on under ZCS condition.Also, the body diode of Sa1,  1 starts to conduct.In this mode, because of the initial voltage of   , which is applied across the leakage inductances, their current increases in the negative direction and thus  2 starts to increase.Therefor,  1 decreases and when  1 reaches  2  ,  1 turns off under ZCS condition at the end of this mode.Mode 11 [t10-t11] (see Fig. 4k): At  10 ,  1 turns off and a resonant circuit is made between   ,  2 ,  1 , and  2 .In this resonance,  2 starts to discharge and  2 increases in a negative direction.At the end of this interval,  2 voltage reaches zero and  2 turns on.
Where  3 = √ Mode 12 [t11-t12] (see Fig. 4l): At the beginning of this mode, by conducting  2 ,  2 can be switched on under ZVS condition.Also, the resonance continues between   ,  2 and  1 and the leakage inductance current decreases.At the end of this mode,  1 and  2 reaches zero, the voltage of   is clamped to (  −   ) and the body diode of  2 turns off under ZCS condition.Therefore, the auxiliary switches can be turned off under ZVZCS.
Mode 13 [t12-t13] (see Fig. 4m): In this mode, both  1 and  2 switches are on and   is applied across both magnetizing inductances  1 and  2 and they are charged linearly.

III. ANALYSIS AND DESIGN CONSIDERATIONS OF THE PROPOSED CONVERTER
In this section, first the voltage gain ratio of the proposed converters are precisely calculated by considering the leakage inductances and are compared with the voltage gain ratio in the ideal form.The design of the components of the proposed converter including the ZVT cell and the main power circuit are presented.Also, in order to select proper MOSFETs and diodes, voltage and current stresses of semiconductor elements are calculated.

A.
Voltage Gain Ratio of the Proposed Converter: In order to calculate the voltage gain of the proposed converter, at the beginning the voltage of the capacitors C1 and Cc should be calculated by volt-second balance relations of  2 and  1 inductors in ( 28) and ( 29), respectively.
Also, by following the same procedure for the second proposed converter in Fig. 2(b), its voltage gain relation is obtained by The ideal voltage gain plot of the first proposed converter with several turns ratio is resented in Fig. 6(a).It is obvious that the turns ratio has a remarkable impact on the voltage gain of the proposed converter.In case of considering leakage inductances, the voltage gain should be calculated more precisely.By considering the average current of the output diode ( () ), the voltage-gain can be derived by considering the impact of leakage inductances.  current starts increasing linearly during mode 2, culminates at  2 , and reaches zero during mode 3. Considering   and   as the rising and falling slopes of   current, and   and   as the rise time and fall time of   current, the following equations can be written.
In equation 38, the peak current of   ( () ) is achieved by (4) based on mode 2, and it is equal to Considering the waveform of the output diode current as a triangle form, the following equation can be written for  () .
Equation ( 40) is dependent on both leakage inductances  1 and  2 .However, due to the very short value of   (  <<   ), it can be ignored and thus the effect of  2 can be neglected in the voltage gain equation.Therefore, the second term in equation ( 40) can be removed and the following equation is achieved between   and   : In ( 42), the factor 2   1 /    2 (1 − ) represents the effect of leakage inductance.Equation ( 42) is depicted via MATLAB software for two values of coupled inductors turn ratio ( = 1 and  = 2) in Fig. 7.Note that the parameters presented in Table II are used for plotting this equation.According to equation (42) and Fig .7, the voltage-gain for no load condition (  = 0) will be equal to the ideal voltage gain relation in (31).It can be inferred from Fig. 7(a) and 7(b) that the voltagegain for duty cycles less than 0.7 is almost constant in the whole range of output power and is less affected by leakage inductance.Also, comparison of Fig. 7(a) and 7(b) illustrates that by increasing the turn ratio (n) of the coupled inductors, the desired voltage gain can be achieved via lower duty cycles.As a result of which, it can be concluded that the more the turn ratio of the coupled inductors (n) is increased, the less voltage gain will be affected by the leakage inductance at nominal loads. .

B.
Components Design

1)
Semiconductor components: According to mode 2, the peak voltage across the main switch  1 , the auxiliary switch   and diode  1 are equal to [  −  1 ], [(  −  1 ) +   ], and   , respectively.Also, according to mode 9, the voltage stress of  2 , diode   and diode   are, respectively, equal to  1 , [  −  1 ], and [V o + V C1 −   ].Replacing equations ( 28) and (30) into the previously mentioned relations, the voltage stress of semiconductor components are achieved and presented in Table .I. Also, the current of   and  2 switches reach the highest value during mode 5 and the current of  1 peaks during mode 11.So, using equations ( 12) and ( 23), the current stress of switches are achieved.
Fig. 8 shows the relationship between the normalized voltage stress of semiconductor components of the first proposed converters versus coupled inductors turn ratio(n).As n increases, the auxiliary switch voltage stress   ,  1 and   increase and in contrast, the main switches voltage stress  1 ,  2 and   are increased.Therefore, the MOSFETs with low  () can be utilized to reduce the conduction losses of the main switches.
Fig. 9 shows a comparison which is made between   voltage stress of the proposed converter and interleaved converters in [22], [23] and [25].As duty cycle raises, the voltage stress of the output diode is increased.Therefore, the maximum duty cycle determines the voltage stress of the output diode.

2) Coupled Inductors Design:
To design coupled inductors, two parameters should be determined, the turn ratio and the magnetizing inductance.The turns ratio of the coupled inductors is a key factor that affects the main switches' voltage stress.Based on Table I, the higher the turn ratio, the less main switches' voltage stress would be.Also, based on the desired voltage gain and considering the point that when D is larger and turn ratio is lower, less power is processed magnetically through coupled inductors, the maximum value of the turn ratio can be designed as follows.
The magnetizing inductances of the coupled inductors determine the input current ripple (∆  ).Considering that the input current has a frequency twice the switching frequency (w), the magnetizing inductances  1 and  2 can be derived as Additionally, the capacitors  1 ,   , and   are designed based on their peak-to-peak ripple voltage; thus, they derived as follows:

3) Resonant Capacitor Design:
In the proposed converter, the resonant capacitor should provide ZVS condition at turn-on for the main switches.Therefore, according to mode 3, 4, and 5 the resonant capacitor should have enough energy to increase the current of  2 from zero to Rewriting equation (48) yields the following limitation on the selection of   capacitor: IV. RESULTS

A. Experimental Results
To verify the performance of the proposed converter and validate its advantages, a laboratory prototype with the specifications presented in Table .II is built.Since in this converter the gate-source of the auxiliary switches  1 and  2 1 is very low (below 1W), so   winding does not take much space.But for further reduction in the volume of   , a voltagedoubler circuit is employed to rectify the pulsating voltage across   .Due to boosting the voltage by voltage-doubler circuit, the number of turns of   coil (  ) is reduced.The positive voltage across   is a ratio of   and the negative voltage is a ratio of (  −  1 −   ).As,   is the summation of  1 and  2 , it is given by Therefor the number of turns of   inductor (  ) is achieved by where,  1 is the number of turns of  1 and   is the required voltage for the auxiliary switches' gate driver, which is typically below 20 V, depends on the type of power MOSFET.The implemented prototype of the proposed converter is presented in Fig. 11 and the experimental waveforms are illustrated in Fig. 12 and Fig. 13.Current and voltage waveforms of the main switches  1 ,  2 and the auxiliary switch   are shown in Fig. 12(a) ,12(b), and 12(c).It is noted that   switch is a series combination of MOSFETs  1 and  2 .As can be seen in these figures, ZVS condition at turn-on and turnoff are achieved for the main switches and the auxiliary switch is properly turned off under ZVS and it is also turned on under ZCS condition.Figures 12(d), 12(e), and 12(f), respectively, show the voltage and current of diodes  1 ,   , and   .The achieved ZCS turn off condition for all three diodes can alleviate reverse recovery effect of power diodes.Fig. 12(g) illustrates the input current   and the current of L m1 and  2 .Due to the interleaved structure, the input current ripple is low, because it is the summation of two parallel modules with 180degree phase shift and thus the current ripple of coupled inductors can be canceled in the input current.Moreover, in are presented in Fig. 13.These waveforms illustrate the capability of the proposed converter in providing soft switching for a wide range of output power.

B. Comparison of the proposed converter with Previous converters
The proposed ZVT auxiliary cell which is highlighted via red box in Fig. 2(a) is compared with the existing ZVT cells used for the interleaved boost structures in [21]- [29], and [31].Comparison results are presented in Table III

C. Circuit startup
There are two main concerns for the startup process of this topology.The first problem is the excessive output voltage overshoot and inrush current at the startup time, which is a common issue among step up boost structures, because the voltage of the output capacitor and the clamp and the multiplier capacitors arezeroat the beginning.By usingsoftstart function that ramps the output voltage in a controlled manner upon startup, excessive output voltage overshoot and inrush current will be controlled [43].The second and the most important concern for the startup process is providing soft switching.For the soft switching at switch turn-off instants, the snubber capacitor reduces the overlap between voltage and current independent of the circuit operation.So, there is no concern for switches turn-off.But soft switching at turn-on is achieved by ZVT circuit.During each duty cycle of the switch,  capacitor charges up to −( −  ) then discharges through resonant network and again charges in a negative direction and its voltage is clamped to ( −  ) to provide soft switching for the other switch.The problem is that during start-up, the clamp and the output capacitors have low voltages and thus the capacitor voltage cannot reach the desired value to provide soft switching.As a result of which, the soft switching at turn-on of the switch is lost and the snubber capacitor discharges through the switch during startup.Losing soft switching at the startup does not affect on the circuit operation and efficiency but the snubber capacitor energy should be low enough in order not to damage the switch during startup time.The energy of the snubber capacitor depends on the value of snubber capacitor (  ), the output capacitance of the switch ( ), voltage stress of the switch and the startup time ( ), during which the capacitor discharges throughout the switch.
This energy should be lower than the maximum power that switches  and  can dissipate throughout their heatsink.Due to the short duration of start-up time which is around 1ms to 10 ms depends on the soft start time [43] and by considering the components in table 2 and equation 50, dissipated energy during startup time of the switch is around 30 mJ, which is negligible and much less than that to cause the switch to burn out.are floating and separate from the main ground of the circuit, an isolated gate-driver is required.There are different options for implementing the isolated gate driver such as opto-isolators.These methods require an extra isolated power supply resulting in lower power density.In this section, an optimized gate driver circuit based on opto-isolators is proposed for driving the auxiliary switches, which is beneficial for specific applications that demand higher power density.The proposed gate-driver circuit is presented in Fig. 10.A small tertiary winding (  ) is employed which is coupled with the coupled inductors  and  to fulfill the need for isolated power source and prevent extra space occupation.The needed power for the gate-driver circuit table the active clamp circuits are not referred, and they are compared in Table IV, because as mentioned in the introduction section, the soft switching condition, which can be provided via active clamp circuits, are load dependent and has * a bidirectional switch implemented via two unidirectional power MOSFETs. 1 Non-Isolated Gate Driver, 2 Isolated Gate Driver limited soft switching range.So, only Zero voltage transition (ZVT) cells which can provide soft switching independent of load for interleaved boost structures are referred in this section.Compared to the other ZVT structures, the main advantage of the proposed ZVT cell is using the minimum number of circuit elements.As can be observed in Table III, only one bidirectional switch is used as a semiconductor element in the proposed cell which is implemented via two power MOSFETs and thus merely a single gate driver is employed; while for the other schemes, three or more semiconductor elements including power switches and diodes are required.This results in low conduction losses of the proposed ZVT cell and the ZVT cell presented in [23].Due to employing the leakage inductance of the power circuit as the resonant inductor, no additional magnetic cores and auxiliary windings are needed for the proposed ZVT cell, whereas at least one auxiliary winding is necessary for other topologies.Having no extra diodes, employing the lowest number of switches and no extra magnetic elements in the proposed ZVT cell are distinctive advantages of the proposed cell.All these factors result in very low conduction losses and high-power density of the proposed ZVT cell.In table IV, the proposed interleaved converters are compared with several similar structures from different aspects.In terms of the soft switching point of view, references [14] and [15] use lossless snubber circuits to create soft switching condition.The ZCS turn-on condition in these converters results in Eoss losses for both main switches.Also, the converter in [15] has only ZCS condition at turn-on instants and turn-off soft switching is lost.Moreover, they lack common ground between the input and output voltage which makes the control scheme more complex.Converters in [16]- [20] employ active clamp technique to provide ZVS conditions for power switches, but the limitation of these converters is the Making use of ZVT cells, the proposed converters along with converters in [21]- [25] create ZVS conditions and guarantee soft-switching in the whole range of output load.The first proposed converter benefits from the lowest number of components among all converters in table II excluding [20] and also it has higher voltage gain than converters in [14] and [24] and similar voltage gain with converters in [21] and [25].The second proposed converter retains the benefits of the first proposed one and have higher voltage gain than converters in [14], [17], [20], [21], [23]- [25] and similar gain with [15] and [18].In comparison to the proposed converters, the circuits in [16], [19] have a bit higher voltage gain and lower switch voltage stress, at the expense of using higher number of semiconductor components but, soft-switching condition is load dependent in these converters.Moreover, the reverse recovery loss is considerable in [19].The only ZVT interleaved converter in table II having higher voltage gain than the second proposed converter is [22].In sharp contrast, it has serious issues like high number of components including nine semiconductor elements and six windings which degrades the power density and total efficiency.In the proposed converters, only two magnetic cores are required, while four separate magnetic cores are used in [14], [18], [21], and [23] which raise circuit volume and losses.To sum up, the proposed converters provide a high voltage conversion ratio with low switch voltage stress and soft switching performance independent of output load and input voltage using minimum magnetic cores and circuit elements.Wide range of soft switching performance dramatically reduces switching losses and provide high efficiency in a wide range.Also, common ground is another noteworthy feature of these converters which simplify the voltage feedback.

C. Power loss and power density analysis in comparison with other converters
Since one of the outstanding features of the proposed ZVT converter is utilizing low number of components as well as low losses at both full loads and light loads, this feature must be investigated.In this section, a detailed losses breakdown is presented for the proposed converter at both full load and light load (20% of the nominal load) conditions and two other ZVT interleaved high step-up converters in [23] and [24] (Fig. 14).OrCAD PSPICE software is used in this section for simulating the mentioned converters and analysis.In Fig. 14, the main and the auxiliary power components including power switches, diodes, and inductors are separately considered and the rest of losses associated with the gate driver and ESR of capacitors are aggregated in the chart under the name of "Others".A-Switches, A-Diodes and A-Windings stand for the Auxiliary switches, diodes, and windings used in each ZVT cell and M-Switches, M-Diodes, and M-Windings denote the main power components of each converter.Note that losses of the main switches consist of conduction losses and switching losses at turn off, because the ZVS condition at turn off is achieved via snubber capacitor and switching losses would not be Fig.14.Loss distribution of the proposed converter in comparison with converters in [23] and [24] at full-load (first rows) and light-load (second rows).Fig. 15.Efficiency of the proposed converter in comparison with the ZVT interleaved converters in [23], [24], and [29].completely zero.For the auxiliary switches which are turned on under ZCS condition, in addition to the conduction losses,   losses are also considered.For the proposed converter, Mdiodes losses are the summation of  1 ,   , and   conduction losses.According to Fig. 14, losses of the auxiliary diodes (Adiodes) of the converters in [24] is of the highest value and have devoted a huge share of losses to themselves, but in the proposed converter and converter in [23] this term is zero.Also, the main diode losses in the proposed converter are lower than converter in [13] because of utilizing fewer power diodes in the proposed topology.The effects of auxiliary diodes are more significant at light loads and it is one of the parameters which causes high efficiency at light loads.This is because the proposed ZVT cell has used no auxiliary diode and only one semiconductor component is utilized.Table V presents the details of conduction losses calculations for the proposed converter at nominal load including switches, diodes and windings losses.In terms of efficiency, the proposed converter is compared with ZVT interleaved converters in [23], [24], and [29] by using computer simulations (PSpice software) and the results are presented in Fig. 15.The specifications of the simulated converters are the same as that of the proposed converter in table II.Note that, IRF150P221 (  =150 V,  () = 3.6 mΩ,   =1.5 nF) is utilized for  1 and  2 switches of the proposed converter and the converter presented in [23] which benefits from lower voltage stresses.Also IPB200N25N3 (  =250 V,  () =20 mΩ, and   = 0.297 nF) and STP20NK50Z (  =500 V,  () =250 mΩ,   =0.328 nF) are, respectively, used for the main switches of the converters in [24] and [29], since they need switches with higher voltage stress.In order to select the proper auxiliary switch and optimizing its losses, two factors including rms current and the voltage stress of the auxiliary switch which result in the conduction loss and the _ losses must be considered.For the proposed converter and converter in [23] due to the low rms current and low voltage stress at turn on instances, IPB200N25N3 (  =250 V,  () =20 mΩ, and   = 0.297 nF) is selected.For auxiliary switch in [24], which has   [23] AND [24] (400, 48  400 ) higher voltage stress, due to the very high rms current of the auxiliary switch it is highly important to select a switch with low drain-source resistance to have a fair comparison.So FDL100N50F (  =500 V,  () =43 mΩ, and   =1.7 nF) is selected.In contrast, for converter in [29] due to having high voltage stress at turn on instant of the switch and thus high   losses, a switch with low output capacitance (  ) must be selected, which is STP20NK50Z (  =500 V,  () =250 mΩ,   =0.328 nF).Note that to have a fair comparison, it is tried to use switches with almost the same cost for the mentioned converters.
As can be observed in Fig. 15, the proposed converter and converter in [23] have the highest full load efficiency which is around 98.7% at 400W output power.In addition, there is no considerable efficiency drop at light loads thanks to the simple ZVT circuit which is around 98%.This is because of the low number of components and low conduction losses of the proposed converter.Despite of providing soft switching condition and removing switching losses, the main issue for the converter in [24] is having high conduction losses for the auxiliary switch which has degraded the efficiency not only at full loads but also at light loads.Also, the converter in [29] suffer from high voltage stress over both the main and the auxiliary switches which has resulted in higher conduction and   losses.Considering the fact that the efficiency of the proposed converter is almost equal to that of the converter in [23] at full loads and it is a bit higher at light loads, the main advantage of the proposed converter over converter in [23] is benefiting from the lower number of power components and employing a simpler ZVT cell with no extra magnetic element and auxiliary diodes.
In addition to investigation of losses breakdown and efficiency, the power density as well as voltage and current stress of semiconductor components are presented in Table .VI.The 3-dimentional prototype of the proposed converter and converters in [23] and [24] are presented in Fig. 16, 17 and 18 to compare power density.For each prototype, the best matched components are chosen based on the current and voltage stress of each converter (Table VI).The power density of the proposed converter is 20% higher than converter in [23] and 10% higher than [24] at 400 W due to having fewer components.For higher output powers, this difference is increased because the auxiliary circuit and extra capacitors and diodes in [23] will highly affect the power density in case of increasing the output power.

V. CONCLUSION .
In this paper, a novel soft switched interleaved step-up converter for distributed generation applications was presented.Utilizing a simple ZVT auxiliary circuit, composed of only one bidirectional switch and a small capacitor, as well as containing the minimum number of power components have made this a highly efficient topology and an appropriate candidate for high power density DC-DC applications.The capability of increasing voltage gain to a desired value with low number of power components, as well as low voltage stress across switches have resulted in low conduction losses for the proposed converter.Additionally, by providing soft switching condition in a wide range of output power and alleviating reverse recovery problems, an experimental efficiency of 98% and a theoretical efficiency of 98.7 % was observed at full load (400 W).Also, at 20 % of nominal load, a theoretical efficiency of 98% was achieved.The power density of the implemented prototype was observed 1.9 W/Cm

Fig. 1 .
Fig. 1.Block Diagram of a grid connected renewable energy system.

Fig. 3 .
Fig. 3.The equivalent circuit of the first proposed converter.

Fig. 4 .
Fig.4.The key waveforms of the proposed converter.

Fig. 5 .
Fig.5.Equivalent circuit for each operating interval of the proposed converter.

6 .
Voltage gain vs. duty cycle a) first proposed converter with different turns ratio (n) and b) comparison of the proposed converters with other converters in

Fig. 6 .
(b) illustrates the ideal voltage gain plot of the proposed converters and five other coupledinductor-based interleaved converters in the literature.In this plot, the turn ratio (n) is considered one and the coupling factor (k) is unity.Note that a detailed comparison of the proposed converter with the existing interleaved converters are presented in section IV.B.

Fig. 7 .
Non-idealized voltage gain ratio of the proposed converter vs. duty cycle and output power considering the impact of  1 , a)  = 1, b)  = 2.Considering the voltage gain ratio of the proposed converter  voltage gain relation is achieved by(42) as a function of duty cycle and the output power, which is affected by  1 .
the curent of  1 from   to  1  during mode 4. Then during the resonance in mode 5, the remained energy of this capacitor should be consumed to reduce the voltage of  1 form   /(1 − ) to zero.As the initial voltage of   capactor is considered   1− the follwing equation should be satisfied.

Fig. 11 .
PCB of the proposed Circuit.a) 3D prototype b) implemented prototype Rewriting equation (48) yields the following limitation on the selection of   capacitor.

Fig. 12 .Fig. 13 .
Fig. 13.Experimental waveforms of the switches at light load (20% of nominal load).(a) main switch  1 (b) main switch  2 (c) auxiliary switch FIG.16.CONVERTER IN [23] A) 3D PROTOTYPE FIG.17.CONVERTER IN [24] A) 3D PROTOTYPE FIG.18.PROPOSED CONVERTER A) 3D PROTOTYPE B) SCHEMATIC B) SCHEMATIC B) SCHEMATIC An Interleaved Soft Switched High Step-Up Boost Converter with High Power Density for Renewable Energy Applications Ramin Rahimzadeh Khorasani, Graduate Student Member, IEEE, Hamed Moradmand Jazi, Nilanjan Ray Chaudhuri, Senior Member, IEEE, Arash Khoshkbar-Sadigh, Member, IEEE, Mahdi Shaneh, Ehsan Adib, Member, IEEE, and Patrick Wheeler Fellow, IEEE ): At the start of this mode, by reaching  1 to the voltage of clamp capacitor (  ),   and   starts to conduct.So,  1 increases and reaches (   do not turn off at  2 , so the operating modes can be examined more generally.Considering the short period of the resonances which occur once the auxiliary switch is triggered, the time duration of this mode is approximately equal to (1 − )  .

TABLE I CURRENT
AND VOLTAGE STRESS OF SEMICONDUCTOR ELEMENTS

TABLE II IMPORTANT
PARAMETERS OF THE IMPLEMENTED PROTOTYPE . Note that in this

TABLE III COMPARISON
OF THE PROPOSED AUXILIARY CELL WITH THE EXISTING ZVT CELLS APPLIED TO THE INTERLEAVED BOOST TOPOLOGIES

TABLE IV COMPARISON
OF THE PROPOSED CONVERTERS WITH OTHER SOFT SWITCHING INTERLEAVED BOOST CONVERTERS MOS: MOSFET; D: Diode; Cap: Capacitor; Win: Winding, T: Total LD: Load-Dependent, LI, Load-Independent C-G, common Ground R.R, Reverse Recovery dependency of the soft-switching condition on the load.

TABLE V CONDUCTION
LOSSES OF THE COMPONENTS USED IN THE PROPOSED CONVERTER

TABLE VI POWER
DENSITY AND COMPONENTS SPECIFICATIONS OF THE PROPOSED CONVERTER AND CONVERTERS IN