A Novel Phase-lock Loop with Feed-back Repetitive Controller for Robustness to Periodic Disturbance in Three-phase Systems

While power networks evolve towards the new concept of smart grids, with the proliferation of power electronics embedded systems and distributed generation, the insurgence of system unbalance and voltage harmonic distortion, become more and more frequent. Also, often a noisy voltage sampling system can produce offsets in measurements. Such imperfections bring challenges to the phase identification using a traditional phase-lock loop (PLL), utilized in the control of all grid connected converters. However, since the imperfections lead to periodic harmonics in the corresponding dq-axis voltages, the repetitive controller (RC) can be useful for harmonic suppression. This paper presents a three-phase PLL using a feed-back RC. Specially, a novel running mean filter has been added to minimize the interaction between RC and the Proportional-Integral (PI) controller in the PLL. Simulation results show that the proposed PLL can track the phase of the three-phase voltage without being influenced by harmonic distortion.


I. INTRODUCTION
More and more power electronics are involved the power networks with development of smart grids including distributed generation. Harmonics introduced by the power converters, short circuits, the unbalanced load among the three phases, as well as the measurement offset and noise may result in variety of harmonics in the dq-axis voltage, and bring challenges for the phase identification using a traditional phase-lock loop (PLL).
Many PLL solutions have been proposed in literature in the past decades. For example, four different structures of threephase PLLs are found and compared in [1], while two threephase PLL systems are compared in [2]. In this paper, the simplest PLL configuration, as shown in Fig.1, is considered as a basis of the proposed implementation.
Considering a reference frame in which the d-axis aligns with the a-axis of the three-phase when the phase angle is zero, and assuming phase a voltage is at its maximum value when the phase angle is zero, if the tracked phase θ (as drawn in Fig.1) equals the phase angle, Uq should equal zero. Since the proportional integral (PI) controller forces the q-axis voltage Uq to be zero in the steady state, eventually, the phase θ equals to the phase angle between the d-axis and the a-axis.
However, the q-axis voltage Uq may contain harmonics, therefore will not be zero even when phase angle θ is correct. In another words, Uq=0 cannot be used as a sign for indicating the correctness of phase tracking. For example, harmonics can be generated in Uq from the following three sources, and these harmonics bring periodic errors in the tracked phase θ of the PLL: 1) if 5 th , 7 th harmonics are present in U * abc, 6 th harmonics will be present in Udq (as well as multiple of the 6 th harmonic in the presence of higher order harmonics in the system); 2) if there is a ground fault on one of the three phases, 2 nd harmonics will be present in Udq; 3) if the voltage amplitudes of any two phases are wrongly measured or in the presence of voltage sags, 2 nd harmonics will be produced in Udq.
Therefore, it is necessary to enhance the robustness of PLL against harmonics or faults with other advanced algorithms [3][4][5][6]. Discrete Fourier Transform algorithms are used for identifying the fundamental frequency in [3,4]. A complex Hilbert filter, is proposed for the PLL in [5].
Alternatively, the PLL in Fig.1 will be able to operate correctly if the PI controller is "blind" for the harmonics and only works to bring the d.c. part of Uq to zero. This harmonic rejection feature can be achieved using a repetitive controller (RC).
RC is originally proposed in 1981 for motor control application in order to track periodic reference [7][8][9][10]. RC is a perfect tool for periodic signals tracking or periodic harmonics rejection. As shown in Fig.2, it memorizes the periodic error with a delay chain z -N , where N is the closest integer of the ratio between the sampling frequency fs and the frequency of the target periodic error. The periodic error is amplified by the gain Grc. The robustness filter Qf(z) is generally a low-pass filter with the function of attenuating the amplitude of the controller gains at high frequency harmonics. In this paper, it is chosen to be a gain in the range of zero to one (called forgetting factor Qrc) providing an equal attenuation at all frequencies. The stability filter Gf(z) is commonly required for removing the phase shift between the compensation action and the target error. Gf(z) needs to be carefully designed to ensure not only the stability, but also higher performance.
Authors in [6] have proposed a feed-forward multi-bandpass filter based PLL configuration. The pass bands of the filter are some selected even harmonics. Although, this multi-bandpass filter is also named RC, it is totally different from the conventional RC as in Fig.2.
The feed-back conventional RC based structure in Fig.3 is instead adopted for this paper. The working principle of the proposed PLL will be discussed in the next section.
Overall, the aim of this paper is to propose a novel PLL which can track the correct fundamental frequency and phase even under extreme conditions such as odd harmonic distortion, single phase to ground fault, two-phase voltage sags, frequency variation and phase jumps. Two main points are considered in the development of the intended PLL:


To enhance the robustness of the PLL in Fig.1 against harmonics in Uq, a feed-back RC as in Fig.3 is proposed to cancel the ripple component in Uq.


To ensure that the RC only cancels the ripple in Uq, the stability filter Gf(z) of the proposed RC is chosen to be a running mean filter Grmf(z) to filter out the d.c. value.
The performance of the proposed PLL is confirmed in the simulation tests.

II. THE PROPOSED PLL WITH FEED-BACK RC
The diagram of the proposed PLL is shown in Fig.3. Theoretically, at steady state, the input of PI controller and repetitive controller (RC) will be zero, whereas the ripple components contained in Uq are stored in RC through the learning process, and are cancelled by the output Uq com of RC. ω0 is the initial value for the output of PI ω.
The equation of the RC in Fig.3 can be expressed as in (1).
Where, Uq err is the input of RC, Uq com is the output of RC. Again, Qrc is the forgetting factor of RC (Qrc∈[0,1]), Grc is the gain of RC, Gf(z) is the robustness filter. N is the closest integer of the ratio between the sampling frequency fs and the fundamental frequency fd of the three-phase voltages.
The PI controller is expressed as in (2). Where, kp is the proportional gain of PI, and ki is the integral gain. Ts is the sampling period, and Ts=1/fs.
As may have been noticed, the parameters free for tuning are the Grc, Qrc of RC, and kp, ki of PI. These parameters can be chosen according to the system stability. Before the stability of the system can be analyzed, it is worth now deriving the equivalent diagram for the proposed PLL with feed-back RC as in Fig.3.

A. Equivalent Diagram and Working Principle of the Proposed PLL with Feed-back RC
The αβ-axis voltages Uαβ * can be expressed as in (3). Where, A denotes the peak value of the three-phase voltages. Phase θ * denotes the actual phase of the three-phase system.
The relationship between Udq * and Udq can be derived from (4) and (5). As shown in (6), the magnitude of Uq depends on A and δθ. [ Since δθ is assumed to be small, sin(δθ)≈δθ is hold. Therefore, q-axis voltage Uq=-Asin(δθ)≈-A• δθ. Based on this conclusion, the equivalent circuit (in discrete form) of Fig.3 can be drawn as in Fig.4.
Again, the Uq * in Fig.4 is defined as in (4). It is the q-axis voltage when the phase used for the αβ to dq transformation is correct. As discussed after (4), Uq * =0 is hold when the αβ-axis voltages are as ideal as in (3), i.e. when the three-phase voltages are perfectly balanced and pure sinusoidal. However, if the three-phase system is not balanced or contains ripple, Uq * will contain ripple as well.
As illustrated in Fig.4, the working principle of the proposed PLL with feed-back RC is to use the RC to track the a.c. part (i.e. ripple part) of Uq * , whereas, the PI controller is used to track the d.c. part (equals zero) of Uq * . Ideally, at steady state, Uq com cancels all the ripple in Uq * , so that the input of PI equals zero, and indicates δθ=0, i.e. the correctly tracking of the phase.

B. Tuning of the Proposed PLL with Feed-back RC
Following the system diagram in Fig.4, the closed loop transfer function Gclosed(z) can be derived as in (7), where Gp(z)=ATs/(z-1).
According to (7), the proposed PLL-RC system can be divided into three parts as shown in Fig.5. The stability can be ensured if each part of the three is designed to be stable [11,12].
In fact, the part 2 in Fig.5 is the closed loop system without the RC. Therefore, the first step of tuning the proposed PLL is to tune the PI controller without considering the RC.
The relationship between the proportional gain Kp, integral gain Ki of PI and the natural frequency ωn, damping ζ is given by (8), which can be derived from the equivalent circuit in Fig.  4 and Fig.5.
The part 1 in Fig.5 is actually the denominator of the RC equation in (1). By substitution z with e jωTs , the term 1-Qrcz -N can be expressed as 1-Qrce -jNωTs . Again, N=fs/fd=1/(Tsfd), Ts is the sampling period. Therefore, the boundary of (1-Qrce -jNωTs ) can be calculated. Its minimum value (1-Qrc) is achieved when NωTs=2πk, k=0, 1, 2…, i.e. ω=2πkfd. Since the design intention is to reject all periodic harmonics at the fundamental frequency and its multiple frequencies, Qrc is chosen to be one for the maximum attenuation, and consequently, the system response will be zero for inputs at the fundamental frequency and its multiple frequencies.
From the discussions above for the part 2 and part 1, we can know that the input and output of the part 3 is bounded. For bounded system, the small gain theorem [13] can be applied to ensure the stability. The part 3 will be stable if (9) is hold (when Qrc=1).

|1-
1+PI(e jωT s)•G p (e jωT s) | <2 In this paper, the natural frequency ωn and damping ζ are chosen to be 62.83rad/s (i.e.10Hz) and 0.791 respectively for the condition when the fundamental frequency fd of the three-phase voltages is 50Hz. Calculating from (8), kp=1 and ki=40. Similarly, when fd=400Hz, choose ωn=314rad/s (i.e.50Hz), ζ=0.791, such that kp=5, ki=1000. The peak value of the fundamental component in the three-phase system A is 100V. Substituting A, kp, ki into PI(e jωTs )Gp(e jωTs ), we can find that  PI(e jωTs )Gp(e jωTs ) is always above zero. Consequently, it can be derived from (10) that the system will be sufficiently stable if (11) is hold.

0<|G rc G f ( e jωT s )|<2[1+PI(e jωT s )•G p (e jωT s )]
Another point need to be considered is that Qrc, Grc and Gf(z) not only affect the stability of the system, but also the performance. As aforementioned, the maximum attenuation of periodic harmonics can be achieved when Qrc=1. The gain Grc mainly affects the converge speed of the RC [14]. The robustness filter Gf(z) is designed to be a running mean filter as below.

C. Running Mean Filter
As described in the working principle in section II-A, it is desired that RC would only react to the a.c. part of Uq * . However, steady state error in the tracked phase θ may occur in the following scenario.
For example, when the fundamental frequency fd of the three-phase voltages varies, a d.c. offset will be present in Uq due to the sudden mismatch between the tracked frequency and 2πfd. Consequently, the sudden voltage error in Uq err will be recorded in the delay chain of RC, and therefore, be cancelled or partly cancelled by Uq com . Meanwhile, PI will also react on this voltage error until the offset is reduced to zero. Eventually, due to the present of a d.c. component in Uq com , Uq will not be zero at steady state, and the remaining offset in Uq is responsible for the steady state error in the tracked phase θ.
To remove the d.c. component in Uq com , the robustness filter Gf(z) is chosen to be the running filter Grmf(z) as expressed in (12), where, z -N Grmf(z) can be understood as the z -N minus a moving average filter, of which the window size is N. Fig.6 shows the magnitude response of GrcGf(z) when Gf(z)=Grmf(z), and Grc=1. As shown, the design satisfies the stability condition given by (11).
The problem of having steady state error in the tracked phase and the effectiveness of the running mean filter will be simulated in section III-E. The performance when Gf(z)=1 and when Gf(z)=Grmf(z) are compared.

III. SIMULATION RESULTS
Simulation tests are carried out to verify the proposed PLL system performance under five non-ideal conditions as follows, including both grids at 50Hz and 400Hz. The control parameters for the tests are defined in Table I. The natural frequency of the PI is chosen to be smaller than fd.

A. Condition 1: Odd Harmonics in U * abc and with Fundamental Frequency (50Hz) Variation
In this test, 10% 5 th and 5% 7 th harmonics are included in the three-phase voltages U * abc as given in (13). The total harmonic distortion (THD) is 11.18%.
{ U a * =100cos(θ * )+10cos(5θ * )+5cos(7θ * ) Where, dθ * /dt=2πfd , again, fd is the fundamental frequency of the three-phase voltages U * abc, and fd varies from 49.5Hz to 50.5Hz during the test. The initial angular frequency ω0 shown in Fig.3 and Fig.4 is set to be 100π rad/s for the 50 Hz system. Fig.7a shows the real dq-axis voltages (i.e. Udq * ) as defined in (4). Fig.7b and Fig.7c show respectively the tracked frequency and phase calculated by the PLL with/without the proposed RC (includes the running mean filter).
The waveforms in Fig.7 confirms the following points:  The 5 th and 7 th harmonics in the three-phase system leads to 6 th harmonics in its dq-axis voltages. However, the d.c. part of the real q-axis voltage Uq * is still zero. This motivates the use of RC to cancel the a.c. component in Uq * .
 The performance is the best when fd=50 Hz, and perfect frequency tracking and zero phase tracking error are achieved. The performance degrades slightly to ±0.17º phase tracking error, as shown in Fig.6c, when fd varies from 49.5 Hz to 50.5 Hz. This is due to the mismatch between the actual period of the three phases and the corresponding fixed value N used in the delay chain.
 The RC is activated at 0s, and starts to take effect after the first period (i.e. 0.02s) (a) When fd=50Hz and N=400 (b) When fd=400Hz and N=50 Fig. 6 Magnitude response of the GrcGf(z) if Grc=1, Gf(z= Grmf(z).

B. Condition 2: Phase c to Ground Fault and with Fundamental Frequency (50Hz) Variation
In this test, the three-phase voltages as in (14) are considered, where, the phase c is missing. dθ * /dt=2πfd, fd varies from 49.5Hz to 50.5Hz during the test. The initial angular frequency ω0 shown in Fig.3 and Fig.4 is set to be 100π rad/s. Fig.8a shows the real dq-axis voltages (i.e. Udq * ) as defined in (4). Fig.8b and Fig.8c show respectively the tracked frequency and phase calculated by the PLL with/without the proposed RC (includes the running mean filter).
It can be seen from Fig.8:  Single phase to ground fault in the three-phase system leads to 2 nd harmonics in its dq-axis voltages.
 The performance is the best when fd=50 Hz, and perfect frequency tracing and zero phase tracing error are achieved. The performance degrades to ±0.4º phase tracing error as shown in Fig.7c when fd varies from 49.5 Hz to 50.5 Hz.

C. Condition 3: Wrong Voltage Amplitude in Ua * , Ub * and with Fundamental Frequency (50Hz) Variation
In this test, the three-phase voltages as in (15) are considered, where, the amplitudes of phase a and phase b are half. dθ * /dt=2πfd, fd varies from 49.5Hz to 50.5Hz during the test. The initial angular frequency ω0 shown in Fig.3 and Fig.4 is set to be 100π rad/s. Fig.9a shows the real dq-axis voltages (i.e. Udq * ) as defined in (4). Fig.9b and Fig.9c show respectively the tracked frequency and phase calculated by the PLL with/without the proposed RC (includes the running mean filter).
Similar to the results in section III-B, the proposed PLL-RC system works better than the original PLL for both frequency and phase tracking when the amplitudes of U * a and U * b are half of the amplitude of U * c.

D. Condition 4: Odd Harmonics in U * abc and with Fundamental Frequency (400Hz) Variation
In this test, the same three-phase voltages as in (13) are considered. However, fd varies from 399 Hz to 401 Hz during the test. The initial angular frequency ω0 shown in Fig.3 and Fig.4 is set to be 800π rad/s for the 400 Hz system. Fig.10a shows the real dq-axis voltages (i.e. Udq * ) as defined in (4). Fig.10b and Fig.10c show respectively the tracked frequency and phase calculated by the PLL with/without the proposed RC (includes the running mean filter).
Similar to the results in section III-A, the RC starts to take effect after one cycle (1/400=0.0025s). The proposed PLL and RC works significantly better than the original PLL for both  frequency and phase tracing for a 400Hz distorted three-phase system.

E. Condition 5: Phase Jump and Fundamental Frequency (50Hz) Variation
In this test, the same three-phase voltages as in (13) are considered. fd also varies from 49.5 Hz to 50.5 Hz during the test as in section III-A. Additionally, a 50º phase jump in the threephase voltages are applied at 0.6s. The initial angular frequency ω0 shown in Fig.3 and Fig.4 is set to be 100π rad/s. The performance of the proposed RC (i.e. Gf(z)=Grmf(z)) is compared with the RC when Gf(z)=1. Fig.11a shows that comparable frequency tracking performance is achieved when with and without the running mean filter Grmf(z).
The advantage of using Grmf(z) can be seen from Fig.11b and Fig.11c for the phase tracking. As shown, large phase offset is present only when Grmf(z) is not used. Again, such phase offset is caused by the d.c. offset in the output Uq com of RC. The phase offset is removed by the proposed running mean filter. Fig.11 also confirms that the proposed PLL with feed-back RC can track the 50º phase jump within 0.04s (i.e. two periods).

IV. CONCLUSIONS
This paper aims at improving the frequency and phase tracking performance of a PLL in distorted three-phase system. Five non-ideal grid conditions are considered in this paper in order to test the effectiveness of the proposed solution, including harmonics in the three-phase voltages, the single phase to ground fault, the two-phase sag fault or sampling error, slight frequency variations, and phase jumps. It is found that certain    Fig. 11 Performance of PLL with the RC (but Gf(z)=1) and the proposed RC (Gf(z)=Grmf(z)) when U * abc have 5 th , 7 th harmonics, during fundamental frequency variation (fd=49.5~50.5 Hz) and during 50º phase jump at 0.6s. harmonics will be generated in the q-axis voltage Uq for these conditions, and the perfect phase tracking can be achieved by controlling the d.c. value of Uq to zero. This motivates the use of a repetitive controller (RC) within a traditional PLL configuration to remove the a.c. component in Uq. Furthermore, a running mean filter based RC is proposed in order to make sure the RC only compensates the a.c. part of Uq.
The tuning of the PI controller and RC in the proposed PLL have been demonstrated according to the stability analysis.
As verified in five selected non-ideal conditions, the proposed PLL with feed-back RC can improve frequency and phase tracking with respect to the traditional three-phase PLL under periodic disturbance conditions. Although the proposed PLL is mainly designed for fixed frequency systems, it works effectively even under slight frequency variations as previously demonstrated.