Phase-Shift Modulation for a Current-Fed Isolated DC–DC Converter in More Electric Aircrafts

This paper discussed an active-bridge-active-clamp (ABAC) topology that is suitable for highpower more-electric-aircraft applications. Though conventional modulation techniques can be applied to ABAC converters, they present drawbacks, such as increased low-voltage (LV) current ripple and limited power transfer capability. To address these problems, a phase-shift-modulation (PSM) scheme is proposed to provide clean dc terminal current at the LV side while maintaining high power transfer capability and efficiency in a wide operating range. The proposed PSM has a complete switching harmonics cancellation on the LV terminals independent of the operating conditions. This results in high quality power without any ac components, thus minimizing passive filtering. In addition, when terminal voltages vary from their nominal values, the proposed PSM can improve the maximum power transfer capability of the ABAC converter compared to the conventional approach. The theoretical claims are validated by both simulation and experimental results on a 10-kW 270-V/28-V ABAC converter.


Phase-Shift Modulation for a Current-Fed Isolated
DC-DC Converter in More Electric Aircrafts galvanic isolation [3]. The DAB also features high efficiency when its input and output voltages are kept at their nominal values. This is benefited from the inherent zero-voltage switching (ZVS) in all the semiconductor devices [4]. However, a large current ripple is usually observed at the low-voltage (LV) terminals [5]. This leads to requirements for large passive filters. In addition, active suppression techniques are required to mitigate potential resonances between LV terminals and LV sources/loads [6]. Different topologies derived from the DAB concept have also been studied. A series-resonant dc-dc converter is analyzed in [7], where all the switches can work under both ZVS and zero-current switching (ZCS) conditions. A hybrid combining an LLC resonant converter and a DAB converter is proposed in [8], where the LLC is responsible for low-power operations while the DAB contributes to high power range. Tapped transformer and resonant tanks are employed in [9] to widen the ZVS range. A fixed-frequency controlled series-resonant converter and its center-aligned modulation are studied in [10], which decouples the voltage gain from the operating power and frequency. However, none of the existing research works can eliminate the LV current ripple effectively. To satisfy the stringent power quality requirements in the more electric aircraft (MEA), a dc inductor can be connected in series to the dc bus of the LV bridge to suppress the current ripple [11]. However, this brings difficulties in current commutation. Therefore, instead of configuring the inductor in series to the LV bus, it can be placed between the LV bridge switching nodes and LV sources/loads. A soft-switched bidirectional half-bridge dc-dc converter is proposed in [12]. This configuration not only reduces the current ripple on the LV terminals, but also enhances the voltage stepup/step-down capability, making the transformer design easier. However, capacitors in the half-bridge circuits need to handle the current flowing through the transformer. This requires capacitors with large current rating, which makes the topology less attractive in high-power applications. Additionally, two inductors can be placed between the LV sources/loads and LV bridges [13]- [15]. This type of current-fed DAB converter can provide interleaved current paths on the LV side, thus lower the requirements for its passive filtering. In [16], another topology derivation, called S-DAB, also has an interleaved structure, which incorporates two half-bridges on the LV side. Diodes are used to achieve ZCS operations. In S-DAB configuration, dc transformer bias can be naturally suppressed without applying active controls [17], [18]. 0885-8993 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
In this paper, a topology named active bridge active clamp (ABAC) is introduced. The term "active bridge" refers to the H-bridge on the primary side of the transformer, and "active clamp" describes the four half-bridge clamping circuits on the secondary. The ABAC topology provides bidirectional power transfer capability and extra degrees of freedom to effectively eliminate the LV terminal current ripple. It is a viable alternative to classical DAB used in MEA applications [15], [19]. In fact, when the single secondary winding structure of the ABAC converter is considered for high-power low-voltage applications, the high current on the LV side requires the paralleling of semiconductor devices. Alternatively, an increased number of transformer secondaries can be introduced to reduce the current stress in each switching devices, thus reducing the requirements in terms of paralleling active devices. Thus, when the ABAC converter is considered for high-power applications, a dual transformer secondary structure can be adopted. It is important to highlight that this configuration does not increase the number of active devices with respect to a single secondary structure at the same power rating. However, it provides an extra degree of freedom that can be used to thoroughly cancel switching harmonics on the LV terminal current under all operating conditions.
Past investigations on modulation strategies for DAB-based current fed converters mainly focused on the phase-shifting pulsewidth modulation (PS-PWM) techniques. In [20], the phase shifts between the LV side half-bridges are fixed at 180°. while the duty cycles vary in order to control the clamp voltages. The clamp voltages determine the voltage magnitude of the quasi-square wave on the transformer LV port. Voltage magnitude on the transformer LV port is manipulated to match with the transformer HV port value to enhance the efficiency. Moreover, an alternative PS-PWM technique where a fixed deviation is imposed between the duty cycles for HV and LV bridges to achieve wider ZVS regions is proposed in [21]. In [22], another degree of freedom was introduced by controlling the duty cycle of the HV bridges independent of LV bridges, with the aim of optimizing the transformer current. Furthermore, the work presented in [16] adapts the concept of trapezoidal current modulation usually used in a DAB [23] to a current-fed type. However, in this approach, maximum power transfer capability [24] is limited. Additionally, an optimization on transformer rms current by breaking the clamp voltage matching principle investigated in [20] was carried out in [25]. However, common issues with aforementioned PS-PWM methods are increased LV current ripple and limited power transfer capability when the terminal voltages vary from their nominal values.
To address these problems, this paper proposes a phase-shiftmodulation (PSM) technique to supply a clean dc LV terminal current. This PSM maintains the switching duty cycles at 50% of the sampling interval. It splits and shifts the active states of devices in one switching period to achieve complementary switching between the two secondaries. As a consequence, the proposed PSM is able to obtain complete inductor current interleaving, eliminating ac components before the LV filter capacitors. Due to fixed switching duty cycles, it can also achieve higher power transfer capability with respect to classical PS-PWM. However, the proposed PSM may cause high transformer current stress. Closed-form expressions of the operating phase shifts trajectories are first derived so that an optimization of the transformer current stress is carried out to the proposed PSM. The ZVS range is also analyzed for the proposed modulation, identifying factors that affect the soft-switching region. By such means, efficiency can be improved, especially when HV and LV voltages vary from their nominal values.
The main contribution of this paper can be summarized as follows 1) drawbacks of conventional PS-PWM techniques for current-fed DAB are quantitatively analyzed;. 2) a PSM modulation technique is proposed for the dual secondary ABAC converter; and 3) transformer current stress and ZVS region analysis are carried out for the proposed PSM technique. It is also important to highlight that the proposed approach can be still applied to other current-fed topologies [13]- [16] in order to expand their maximum power capability when operating under voltage conditions that differ from their nominal values. In addition, when enough degrees of freedom are provided, complete current ripple cancellation can be achieved with the proposed method.
The paper is structured as follows: In Section II, the ABAC operated with PS-PWM is described, and the issue of increased LV current harmonics when dc voltages are not at the nominal values is analyzed. In Section III, a PSM technique is proposed that overcomes the limitations of PS-PWM. Operation analysis is conducted, and maximum power transfer capabilities of both PSM and PS-PWM are derived and compared. Moreover, transformer current stress is optimized, and a closed-form expression of the operation trajectories is derived. Finally, ZVS constraints for the ABAC converter are derived and discussed. Simulation and experimental results are presented for a 10-kW ABAC, reported in Sections IV and V, respectively. Section VI concludes this paper.

II. ABAC CONVERTER STRUCTURE AND CONVENTIONAL MODULATION TECHNIQUE
The ABAC topology is presented in Fig. 1. A three-port highfrequency transformer with turn ratio N:1 is used. A full-bridge circuit, associated with the high-voltage side of the converter is connected to the primary winding of the transformer and generates the voltage v ac1 . On the LV side of the transformer, two interleaved half-bridge clamp circuits are connected to each secondary through power transfer inductors L s . The two secondary circuits are able to work independently, generating different voltages v ac2 and v ac3 . However, in applications where equal power sharing is required between the two secondary ports, the condition v ac2 = v ac3 is imposed. C c are the clamp capacitors that serve as an energy buffer between the transformer and the LV load. L o are the output filter inductors, used to suppress the current ripple. Finally, the LV current I LV is filtered by LV capacitor C o before flowing into the LV load R L .
There are several modulation schemes available for the ABAC converter [16], [22]. However, these techniques present two , G 10 = not(G 9 ), and G 12 = not(G 11 ). 0 < D d T < 0.5. main issues when V H V or V LV vary far from their nominal operating values. The first issue is that maximum power transfer capability is reduced. This will be discussed in Section III-B. Another issues is that they present large current ripple on I LV , which can increase the requirement on passive filtering and potentially introduce resonance between the LV terminal and the LV source/loads [6]. As an example, one of the PS-PWM techniques [20] is discussed herein for the ABAC converter, as depicted in Fig. 2.
Considering the structure of the ABAC converter in Fig. 1, the power transfer inductance L s is placed on the LV side in order to provide decoupling between the two transformer secondaries. Due to this design constraint, in high-power applications the value of L s is usually of few hundreds of nH [15]. As a consequence, inductance with litz wires [26], in combination with the leakage inductance of the transformer, can be used to implement the power transfer inductance.
In the PS-PWM scheme shown in Fig. 2, the inner phase shift between G 1 and G 3, G 5 and G 7 , and G 9 and G 11 , is always fixed at π. Therefore, LV inductor current pair i L 1 , i L 2 and i L 3 , i L 4 are interleaved with a phase shift of π. The outer phase shift ϕ between G 1 and G 5 (G 9 ) is used to control power transferred between transformer primary and secondary ports. The duty cycles of all switches are fixed at D dT . Referring to Fig. 2, the relationships between the duty cycle of the transformer quasi-square wave voltages D d and the duty cycle of switches D dT are expressed as follows: Clamp voltages (v c1 − v c4 ) are controlled by the duty cycle D dT . If clamp voltages are designed to match with the primary transformer voltage magnitude V H V /N , the voltage ratio r V can be calculated as The use of the PS-PWM can reduce the transformer current stress and its rms value [22]. Additionally, the ZVS operating region can also be expanded [21]. When D dT = 0.5, the current ripples on LV currents i L 1 − i L 4 are well cancelled and I LV is free of switching ripple. However, when D dT = 0.5, as shown in Fig. 2, the current ripple cancellation for i L 1 − i L 4 is compromised. Analysis is carried out here to evaluate the peak-to-peak variation of current I LV when D dT = 0.5. In the steady state, the following equations are satisfied: where I LV is the dc component of the load current I LV , and f s is the switching frequency. L o is the LV side output filter inductance. Substituting (2), (4)-(6) into (3), and conducting similar calculations for operation 0.5 < D dT < 1, expressions for ΔI LV are According to (7), transformer turn ratio N is usually designed to match the following condition: where V * H V and V * LV are nominal voltages. In this case, ΔI LV is equal to zero. It can also be observed from (7) that ΔI LV is increased when V H V or V LV vary from their nominal values. This results in higher requirement for LV side passive filters to suppress the harmonics from propagating into LV terminal dc networks.

III. PROPOSED MODULATION TECHNIQUE
In order to solve the issues discussed in the previous section, a phase-shift-based modulation scheme is introduced in [27]. However, this method may present dc offset to transformer and deviation to inductor current dc values when applied to the ABAC converter. Therefore, an improved PSM is proposed here, as shown in Fig. 3. The duty cycle of the switches is fixed at 50% irrespective of the converter voltages and power. As can be seen from Fig. 3 and considering G 7 as an example, the sum of the active period in one switching cycle is π. The active time of G 7 is split into two parts in period θ 7 − θ 15 . The first part is shifted to the start of this switching period while the second part is shifted to the end of this switching period. Therefore, signals G 7 and G 9 are complementary. It is important to highlight that since the switches T 7 (driven by signal G 7 ) and T 9 (driven by signal G 9 ) are always complementarily switched, therefore the LV currents i L 2 and i L 3 are always interleaved. The same behavior can be observed on switches T 5 and T 11 . Therefore, I LV is ripple-free at any operating points. However, the inductor currents have now an increased period of 2T s in the proposed PSM, as the shape of the inductor currents is defined by the gating signals G 5 -G 11 . In addition, the clamp circuits determine the transformer secondary port voltages v ac2 and v ac3 . In particular, G 5 , G 7 and G 9 , G 11 are used to generate v ac2 and v ac3 , respectively. According to the driving signals, the transformer secondary voltage v ac2 can be generated as v ac2 = v c1 G 5 − v c2 G 7 , while the phase-shift value ϕ is related to the phase shift between G 1 and G 5 . From  Fig. 3, it can be noted that, in a half-switching cycle, the pulse duration in both voltages v ac1 and v ac3 (v ac2 ) present the same value of πD d , where D d can vary from 0 to 1. On the other hand, the outer phase shift between transformer primary and secondary voltages ϕ can vary from 0 to 2π. With this modulation scheme, D d and ϕ can be independently controlled in order to optimize the operation of the converter.
, G 10 = not(G 9 ), and G 12 = not(G 11 ). Operating modes I-IV are discussed below in "A. Operation analysis" and summarized in Table II. There are many ways to generate the gating signals for LV side switches. The proposed PSM requires the generation of variable phases for LV side bridges between two adjacent switching periods. The proposed gating signal generation is shown in Fig. 4, where counters for each EPWM module are independently driven. Counters are compared with a fixed value equal to 50% of the counter maximum C max to generate ON/OFF signals G 1 -G 12 . EPWM4-EPWM7 are responsible for generating the driving signals for the secondary switches T 5 -T 12 , respectively. Since each leg is complementarily switched, only the gates of the upper switches in each half-bridge are shown in Fig. 4. The red dashed lines in Fig. 4 represent the boundary, where phase updates are taken place. Phase updating values for each EPWM counters are listed in Table I and EPWM7A (G 11 ) always have a phase difference of π, as the same for EPWM5A (G 7 ) and EPWM6A (G 9 ). Therefore, 180°p hase shifts between i L 1 and i L 4 also i L 2 and i L 3 are guaranteed and comprehensive LV terminal current ripple cancellation can be achieved.
The main difference between proposed PSM and PS-PWM can be summarized as follows. In the proposed PSM scheme, the duty cycle over one switching period for the LV side clamp switches is fixed at 50% and the clamp circuits operate similarly to an interleaved boost converter. Thus, at a steady state, V c = 2 V LV can always be obtained. The asymmetrical duty cycle of T 7 and T 11 is complementary to the duty cycle of T 9 and T 5 . As a result, inductor currents i L 1 − i L 4 present complementary ac components and complete ripple cancellation. On the other hand, using the classical PS-PWM method, the duty cycle of the LV side switches are used to control the clamp voltages accordingly to the variation of the HV terminal voltage V H V . This results in different power transfer capability and LV terminal current quality when the two modulation techniques are compared, as shown in the following sections.

A. Operation Analysis
Due to the 2 degrees of freedom available, four operating modes are possible, as shown in Table II. As an example, oper-ating mode IV is taken into consideration during the analysis, accordingly to the waveforms shown in Fig. 3(a). Since the transformer current i s2 is symmetrical, only half of the switching cycle, from θ 0 − θ 4 in Fig. 3(a), is analyzed. A typical operation stage analysis in Mode IV with equivalent circuits is shown in Fig. 5.
The analysis considers switches with no parasitic capacitances and dead times, and the stages are described as follows.
Stage 1 (θ 0 − θ 1 ): At θ 0 , T 1 is switched ON while T 2 is switched OFF. Current is commuted from the body diode of T 2 to T 1 . With the increase of i s2 , natural commutation happens from the body diode of T 6 to T 6 and also from T 9 to its body diode. During this period, the transformer secondary current i s2 (θ) can be calculated as Stage 2 (θ 1 − θ 2 ): At θ 1 , T 5 /T 12 is switched ON while T 6/ T 11 is switched OFF. Current is commuted from T 6 to the body diode of T 5 and from T 11 to the body diode of T 12 ; hence, T 5 and T 12 are soft switched. During this period, the transformer secondary current i s2 (θ) can be calculated as where V c is the clamp capacitors voltage in the steady state.
Current is commuted from T 4 to the body diode of T 3 ; hence, T 3 is soft switched. With the decreasing of i s2 , natural commutation happens from T 3 /T 5 /T 9 body diode to T 3 /T 5 /T 9 . During this period, the transformer secondary current i s2 (θ) can be calculated as Stage 4 (θ 3 − θ 4 ): At θ 3 , T 7 /T 10 is switched ON while T 8 /T 9 is switched OFF. Current is commuted from the body diode of T 8 to T 7 . Current is also commuted from T 9 to T 10 body diode; hence, T 10 is soft switched. During this period, the transformer secondary current i s2 (θ) remains unchanged. Therefore Due to symmetrical operation Then, substituting (9)-(12) into (13), currents i s2 (θ 0 ) − i s2 (θ 4 ) are derived and summarized in Table II. The power transferred for a dual secondary structure can be calculated as where D ϕ is defined as ϕ/π. Furthermore, by imposing constraints (1) and (2), results in Table II are also applicable to PS-PWM, shown in Fig. 2. The transferred power is expressed in per-unit with the base power P base defined as Where conditions V c = V H V /N and V c = 2 V LV are applied to PS-PWM and PSM, respectively, the base power for the two modulations under analysis are Similarly, the LV side currents can be expressed in per-unit, with the base I base defined as Similar calculations can also be conducted for other modes (I, II, and III), and results for buck operation (power transferred from the HV bus to the LV bus) are summarized in Table II. For boost operation, the same approach can be applied. However, detailed analysis is omitted in this paper for brevity.

B. Maximum Power Transfer Analysis
The power contour plot P (D d , D ϕ ) for the ABAC converter is shown in Fig. 6 according to Table II, considering all four modes of buck operation. When D d = 1, ϕ = π/2, maximum power can be delivered using PSM. On the other hand, when the ABAC converter is modulated with PS-PWM, D d is related to the voltage ratio r V , as indicated in (1) and (2). For such reason the condition D d = 1 is not always achievable for PS-PWM.
Referring to Fig. 6, the maximum transfer power for both modulations can be expressed as follows by combining (1), (2),  Table II: In order to compare power transfer capability of the two modulations under analysis, a maximum power ratio is defined in in the following as the ratio between the maximum power achievable with PS-PWM and PWM considering the same design parameters, respectively: The same equation is plotted in Fig. 7 as a function of the voltage ratio r v . The PSM approach has the ability to deliver more power than PS-PWM when r V is lower than 0.25 or higher than 0.5.
The ability of providing full power over a wide operating range is a key requirement in aerospace applications. For example, when the more-electric-aircraft concept is considered, the bus voltages may present wide variations with the voltage ratio r V typically having a range from 0.36 to 1. In fact, the EN2282 standard is usually considered for the LV bus, with voltage variations ranging from 22 to 30 V. For the HVdc bus, standard MIL-STD-704 describes a normal operating condition range of 250-300 V. However, the voltage variation can be even larger, since standards are currently under definition for civil moreelectric-aircraft and converter operation with degraded performances may be required at lower voltage values. Additionally, the converter has to be able to provide the full power for a certain amount of time when a short-circuit fault happens on dc buses to allow the circuit breakers to operate [28], [29]. This requirement can also be applied to solid-state power controllers (SSPC), as for example, the SPDC130D28 from sensitron semiconductor [30], which usually use its I 2 t curve to trip operations in the case of fault. In the presence of dc short-circuit fault, the dc bus voltage will drop, and it is essential for the ABAC converter to still be able to provide enough current to allow the SSPC to operate properly.

C. Current Stress Minimization
It can be observed from Fig. 6 that there are several combinations of D d and ϕ/π able to transfer the same power through the converter. This redundancy allows to obtain higher efficiency and power density if optimized solutions are considered. Amongst all the possible targets for this optimization, the transformer current peak value represents a viable parameter to minimize in order to achieve higher efficiency and reduce the HF transformer weight and volume. The transformer current peak value is defined as Based on (22), the transformer current peak value is minimized as follows: Objective : MinI peak Subject to : The obtained results for buck operation are expressed as The minimized transformer current peak value trajectories are plotted in Fig. 8 together with the normalized power contour. In operation modes I and II (illustrated in Fig. 6), high current stress on the transformer can be noted. Therefore, operation in these two modes is avoided following the designed trajectories. All the trajectories are confined within operation modes III and IV, characterized by a lower transformer current peak value. When HV and LV match (r V = 0.5), the minimum current stress trajectory coincides with the line D d = 1, indicating that the phase-shift-modulated-single-phase-shift (PSM-SPS), also known as D d = 1 mode" in [25], can achieve minimal current stress. With the variation of r V from 0.5, the minimum transformer current stress trajectory shows different trends. Fig. 8 considers only buck operations (ϕ > 0). However, when boost operation (ϕ < 0) is considered, symmetrical trajectories, with respect to the x axis of Fig. 8, can be obtained.

D. ZVS Analysis
To simplify the ZVS analysis, the dead time is neglected, as well as the parasitic capacitances of the devices. Therefore, in this approximated analysis, ZVS occurs when the current flows through the body diode of the device when turning it ON. Thus, constraints to achieve ZVS for both HV and LV bridges are summarized in Table III, where I (0) s2 − I (3) s2 are normalized variables, representing secondary transformer current values at the switching instants, as illustrated in Fig. 3.
The utilization of the PSM scheme leads to expressions of the inductor current that are different from the ones proposed in [14]. Therefore, inductor current i L 1 − i L 4 values at switching where I (0) L are normalized variables, representing inductor current values at switching instances, as illustrated in Fig. 3. Values of currents are all normalized to I base as in (18), and m is defined as the ratio between output inductance and power transferring inductance as If the operation of the converter is assumed to follow the minimum transformer current stress trajectories, by substituting equations in Table II, (24)-(26) into the ZVS constraints in Table III, the ZVS region can be derived. It is important to highlight that the ZVS regions depend only on r V , ϕ, and m. In Fig. 9, the ZVS area is plotted as a function of r V and ϕ/π, when m = 3.3. The HV bridges can achieve ZVS for the whole operating range with r V values smaller than 0.5, whereas LV bridges can achieve wider ZVS region for values of r V higher than 0.5. The overlap between these two ZVS regions correspond to soft-switching of the whole converter when m equals 3.3 (practical values of L s = 0.5 μH, L o = 1.65 μH are considered), and it is shown in Fig. 9(c).

IV. SIMULATION RESULTS
The simulation diagram is shown in Fig. 10. A proportional Integral (PI) controller for LV voltage regulation drives the optimized PSM scheme. In fact, even if several different control  techniques can be applied to the ABAC converter, the work in this paper focuses only on modulation techniques and, for such reason, a simple PI control scheme has been considered. The PI controller design has to take into account the different modes of operation and voltage ratio r V . For example, a transition between Mode III and Mode IV results in different small signal models for the ABAC converter and, as a consequence, different sets of PI parameters have to be considered. Similarly when the voltage ratio r V changes, the small signal model for the ABAC converter also changes and the PI controller needs to be retuned. However, the control tuning does not affect the analysis carried out on the proposed modulation and, for such reason, the PI controller parameters have been empirically obtained in each operating point.
The converter parameters are listed in Table IV and correspond to those of the experimental converter discussed in Section V, where P c represents the power transfer capability under all the voltage operating conditions. Simulation results are obtained using a Plexim PLECS software.
Substituting the values from Table IV into (7), the contour plot of ΔI LV can be drawn, as shown in Fig. 11. It can be observed that when V H V = 300 V and V LV = 22 V, a maximum peakto-peak ripple of 71.1 A on I LV is predicted when using PS-PWM. This is confirmed by the simulation shown in Fig. 12(b).  Fig. 11. Contour plot of LV current peak-to-peak value ΔI L V according to (7) using practical parameters from Table IV. However, when PSM is utilized, as illustrated Fig. 12(a), an LV current ripple is effectively cancelled, and there is ideally no need for any passives to filter the current I LV . This feature gives the ABAC converters an advantage in applications, where batteries or fuel cells are integrated on the LV terminal. It is worth mentioning that due to the shape of the inductor currents is controlled by the gating signals G 5 − G 11 , different adjacent active state periods of G 5 -G 11 make the inductor current ripple varying between single sampling intervals T s . Therefore, by using the proposed PSM technique, the inductor currents present repetitive waveform every two sampling intervals (i.e., every 2T s ) rather than one. This is the consequence of applying the proposed modulation, which helps to achieve complete ripple cancellation on I LV . When an MEA application is considered for the ABAC converter, V H V can typically change in a range 150-300 V while V LV can vary from 22-30 V. Therefore, the range for the voltage ratio r V is 0.36-1. According to Fig. 7, in this practical range, PSM has a greater advantage in transferring more power when r V gets close to 1. For example, considering a case when V H V = 150 V, V LV = 28 V and the voltage ratio r V is equal to   (19) and (20), the maximum transfer power for PS-PWM is 160 W while it is possible to transfer 8.4 kW using the proposed PSM. Simulations are shown in Fig. 13. Notably, the duty cycles for both transformer port voltages in the case of PS-PWM are very small. This essentially limits the maximum transferred power. However, in the case of PSM, the duty can be modified accordingly with the power.
A transition between Mode IV and Mode III is shown in Fig. 8, where the trajectory lines are all linear and continuous across two modes. As mentioned at the beginning of this section, due to the converter model changes between Mode III and Mode IV when power changes, different sets of PI parameters are required to ensure performance. However, the voltage control has been implemented considering, on purpose, a very small control bandwidth. This has been required with the only scope of providing accurate steady-state results, with slow dynamic performances and negligible disturbance rejection since the paper focus only on modulation and the control dynamic performances are not considered in this paper. In this simulation, HV and LV are connected to 300 V and 22 V voltage sources, respectively. As can be observed in Fig. 14, the transition between modes is smooth.
Finally, losses for all the active devices including HV side and LV side switches are evaluated. The components in Table V are used in both simulation and experiment. Losses are estimated in PLECS based on datasheet parameters.
Semiconductor losses under four different input/output voltage conditions on the whole converter power range are evaluated. It is worth pointing out that the loss evaluation is only meant to compare different modulation schemes rather than to provide an accurate overall efficiency prediction for this converter. The evaluation comprises both switching and conduction losses. Comparisons between modulations PS-PWM [20], PSM-SPS [25], PS-TRM [27], and PSM are carried out based on the same design parameters. According to p1 and p2 in Fig. 15, PS-PWM presents the advantage over other schemes in terms of losses from switching devices. This is expected as in the case of PS-PWM, transformer current is lower in both the peak and rms value than others [22]. The increase in loss compared to PS-PWM is the major shortcoming of PSM. However, under voltage operating points p3 and p4, the conventional PS-PWM approach can hardly transfer any power, and PS-PWM cannot achieve comprehensive LV current ripple cancellation. It is worth pointing out that the power transfer capability of PS-TRM [27] relies on the difference between primary and secondary port voltages. As can be seen from p1 and p4, PS-TRM has larger maximum power transfer capability compared to p2 and p3. Additionally, it can be observed that the optimized PSM generally has fewer losses than PSM-SPS under light and medium power in p1 and p2. According to the loss evaluation, a hybrid modulation scheme is possible for future investigation, but this paper focuses only on the proposed PSM, emphasizing on the comprehensive LV current ripple cancellation and enhanced power transfer capability.

V. EXPERIMENTAL RESULTS
The proposed modulation has been validated on a 100 kHz, 270 V/28 V prototype, shown in Fig. 16. Semiconductors listed in Table V have been also used in this prototype. A TMS320F2837xD evaluation board from Texas Instruments, enhanced by a custom interface board, has been adopted as the digital control platform. The LV terminal voltage is measured and controlled by a PI controller, as discussed in Fig. 10. Results are sampled with a LeCroy oscilloscope using 100-MHz bandwidth differential voltage probes and 10-MHz bandwidth current probes. Results have been plotted using MATLAB in order to provide clearer waveforms and to facilitate analysis.
Experimental results are shown in Fig. 17, where the ABAC is modulated with PSM-SPS to deliver a power of 10 kW to the LV resistive load, in the nominal voltage condition. The primary, secondary port voltages and secondary, primary transformer currents, together with the LV terminal voltage are shown from top to bottom in Fig. 17. The V LV is well regulated with a 550 mV peak-to-peak ripple.
Experimental results using optimized PSM are shown in Fig. 18(a) highlighting the balanced output inductor currents and the absence of transformer dc bias, compared to the modulation method presented in [27]. The terminal voltage condition is V H V = 170 V, V LV = 28 V whilst providing 3 kW on a resistive load. The dc components of current i L 3 and i L 4 are  balanced according to the waveform of I L 3 − I L 4 . Also there is no dc bias current on the transformer, as confirmed by the i s2ac waveform. Experiment results highlighting the LV currents interleaving feature of the proposed PSM scheme are shown in Fig. 18(b). In the experiment, the ac components of the LV current are measured as I LV ac . It is clear from the figure that effective LV ripple cancellation is achieved between i L 1 , i L 4 and i L 2 , i L 3 . As a consequence, the V LV peak-to-peak ripple is limited to 540 mV. It is worth mentioning that under such operating voltage condition, the conventional approach PS-PWM [20] can hardly transfer any power.   In accordance with the proposed PSM in Fig. 3, the inductor currents have a period of 2/f s . Therefore, the shapes of i L 3 and i L 4 are balanced in two switching cycles. Regarding the transformer current, in the period θ 3 -θ 5 and θ 7 -θ 9 , the capacitor C 1 and C 2 are inserted in the circuit together. However, in the period 0-θ 1 and θ 11 -θ 13 both capacitors are floating. Therefore, due to voltage variations on clamp capacitors, the shape of i s2 is different in period θ 3 -θ 5 and θ 7 -θ 9 from the shape in the period 0-θ 1 and θ 11 -θ 13 . Notably, the waveform of v ac3 has some discrepancies compared to the one obtained in Figs. 12(a) and 13(a), and it presents additional voltage steps on v ac3 when the slope of the transformer current changes. These are caused by parasitic grounding inductance between four clamp circuits in the prototype, and this effect can be removed by changing the physical layout of the clamp circuits.
Comparisons of transformer current stress between PSM-SPS (also known as "D d = 1 mode" in paper [25]) and optimized PSM under different voltage ratio r V are shown in Fig. 19. It can be noted that when using optimized PSM, the transformer current stress is always smaller than PSM-SPS, especially when the load power is decreased and operation voltage varies from the nominal value. However, when operating voltages become close to the nominal value, the optimization on peak current presents negligible advantages, as already shown in Fig. 15.
Experiment results in Figs. 20 and 21 show ZVS validations for points A and B in Fig. 9. The waveforms are obtained under r V above 0.5 in Figs. 20(a) and 21(a) and for r V close to 0.5 in Figs. 20(b) and 21(b). As predicted by the theoretical analysis, currents are always flowing through the anti-paralleled body diode of the MOSFETs before being turned ON. Therefore, ZVS can be achieved for all switches in both cases.

VI. CONCLUSION
In this paper, the ABAC converter is introduced as a suitable power converter topology to transfer power between 270VDC and 28VDC buses in high-power MEA applications where stringent power quality requirements apply. Conventionally, the ABAC converter can be driven with PS-PWM techniques. However, PS-PWM presents increased LV current harmonics and less power transfer capability when HV and LV vary from their nominal values. Therefore, a PSM is proposed and optimized. By using the proposed PSM in this paper, maximum power transfer capability can be greatly improved compared to PS-PWM. It can also achieve comprehensive cancellation on LV current at any voltage operation points, resulting in lower requirements for passive filtering when compared to the PS-PWM.
Simulations and experiments on a 10-KW ABAC converter are conducted to verify the theoretical claims. A comparison between the presented PSM and PS-PWM has been carried out. The results show the advantage of the proposed method in terms of LV power quality and power transfer ability. In addition, analysis and validation of the ZVS region are also provided. Comparisons between optimized PSM and PSM-SPS are also conducted, confirming the merit of transformer current stress reduction using the proposed method.