A Switched Mid-Point Modular Multilevel Converter for HVDC Applications

The modular multilevel converter (MMC) has emerged as the industry standard for voltage source converters (VSC) based high voltage direct-current (HVDC) applications since its benefits of scalability, modularity, high efficiency and better output quality outweigh its drawback of large energy storage. However, with a growing number of offshore HVDC installations, the volume and footprint of the converter, which are largely influenced by its energy storage, are becoming increasingly critical. This has led to a rising interest in alternative converter topologies that reduce the energy storage while maintaining the benefits of the MMC. This paper introduces a switched mid-point modular multilevel converter (SMPC), that is able to generate the desired AC-side waveforms with significantly less energy storage (around 50%) than the MMC. The DC-side is free from any distortion that requires additional filtering. Reduced energy storage and the associated reduction in volume is achieved at the expense of requiring more switches and slightly lower efficiency when compared to the MMC. Like many other MMC-style circuits, except when operating at a ‘sweet-spot’, active control of the energy balance is needed, for which a technique based on second harmonic injection is proposed. The converter operation and the proposed control scheme are verified by simulations for a medium-voltage setup and experimentally on a low-voltage lab-scale prototype.


I. INTRODUCTION
V OLTAGE source converter (VSC) based High Voltage Direct Current (HVDC) transmission has significant benefits over the traditional Line-Commutated Converter (LCC) based HVDC systems, such as independent control of active and reactive power, connection to weak AC systems, black-start capability, and lower harmonic filtering requirements [1], [2]. Due to its benefits, VSC-HVDC is extensively used for power transmission from offshore wind farms and is expected to play a pivotal role in the interconnected DC "supergrids" of the future [3]. A main element of a VSC-HVDC system is the AC-DC converter that takes up the majority of the initial set up cost, and therefore, there has been huge interest lately in improving these converters in terms of physical size, functionality, cost and efficiency.
In offshore wind applications, the size of the HVDC converter platform significantly influences the overall system cost [4]. Moreover, there is a rising demand for HVDC in city center infeeds where land area is at a premium [5]. Thus, due to the growing use of HVDC converters in space-constrained applications, there is considerable interest in making these converters more compact to minimise overall system costs.
Recently, in the field of VSC-HVDC, modular type multilevel converters have attracted significant attention. In particular, the Modular Multilevel Converter (MMC) has been widely commercialised by HVDC manufacturers. Introduced in 2001 [6], the distinctive feature of the MMC is the series connection of identical submodules which makes it easily scalable to high voltage levels. In addition, the MMC also features low switching losses, low dv/dt and high quality output waveforms [7], [8], [9]. However, the disadvantage of the MMC is the high energy storage requirement [10], which directly affects the cost, volume, weight and footprint of the converter [11]. Thus, an HVDC converter that offers the same functionality as the MMC but with a lower energy storage is likely to be more attractive for space-critical applications.
In recent years, a new breed of VSC converters, that combine the features of the two-and three-level converters with the modular structure of the MMC, have been introduced.
The Alternate Arm Converter (AAC) [12], [13], [14] is one such promising topology for HVDC applications with inherent DC fault blocking capability due to its cells being formed of full bridges. With the help of director switches, the upper and lower arms of the AAC are made to conduct alternately during each half cycle, thereby reducing the voltage ratings of the arm to one-half of that in the MMC. However, the disadvantage of the AAC is the need for a large DC bus filter [15]. An improved variant of the AAC is the Extended-Overlap AAC (EO-AAC) [16] which eliminates the need for the DC bus filter at the expense of a higher number of semiconductor devices.
To reduce the number of submodules, various topologies with a series connection of converter phases have also been introduced. Among them, the most prominent are the Parallel Hybrid Modular Multilevel Converter (PH-MMC) [17], [18] and the Series Bridge Converter (SBC) [19], [20]. Due to the coupling between AC-and DC-side voltages in the PH-MMC resulting in a fixed modulation index, the control of the AC 0885-8977 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information. output voltage is achieved by adding third harmonic components in the reference voltages [17]. The SBC is an extension of the PH-MMC, in which the AC and DC sides are decoupled by employing additional arrays of full bridge cells. Both the PH-MMC and the SBC require almost half the number of submodules and a smaller energy storage compared to the MMC, thereby providing a sizeable reduction in volume and weight. However, similar to the AAC, large DC side filters are needed in both the PH-MMC and the SBC. The series chain-link converter (SCC) [21] is another topology that has the same energy storage as the MMC, but it is distributed more compactly due to a lower submodule count. This article introduces a switched mid-point AC-DC converter (SMPC) intended for HVDC applications with the aim of providing the same functionality as the MMC with a smaller energy storage requirement. Unlike other hybrid multilevel converters, the voltage synthesis of the SMPC arms is such that there is no requirement for bulky DC-side filters.
The rest of this article is organised as follows. Section II introduces the basic operating principle of the SMPC and describes the voltage wave-shaping of the chainlinks (CLs). The energy management of the SMPC and the proposed method for arm energy balancing is discussed in Section III. The matter of selection of the nominal modulation index of the converter is addressed in Section IV. Section V details a comparative analysis against the MMC and other hybrid multilevel topologies. In Section VI, the control scheme for the SMPC is explained and simulation results are presented in Section VII. Description of the small-scale prototype and experimental results are presented in Section VIII.

II. DESCRIPTION OF THE TOPOLOGY
A schematic of the proposed converter is presented in Fig. 1. The converter phase-legs in the SMPC are connected in parallel across the DC side. Each phase-leg consists of a director switch (DS) configuration, two arm reactors and three waveshaping chainlinks (CLs) namely upper (UPP), middle (MID) and lower (LOW) CLs. The DSs are switched at AC line frequency and to achieve sufficient voltage ratings, the DSs are composed of a series string of IGBTs. To avoid a short-circuit through the anti-parallel diodes of the DSs, a negative voltage cannot be allowed across the MID CL terminals. Hence, the MID CLs are required to produce positive voltage levels only and are formed by a series connection of half-bridge (HB) cells. As will be shown in the subsequent sections, for the internal energy of the converter to naturally balance, the modulation index, i.e. the ratio of the peak AC voltage to half the DC voltage, is π 2 which requires the converter to operate in over-modulation. For this reason, the UPP and LOW CLs are required to synthesise both positive and negative voltage levels. It is possible to construct the UPP/LOW CLs with two possible formations -(1) a series connection of full-bridge (FB) cells and (2) 'hybrid chainlinks' that are formed by connecting both HBs and FBs in series in the same chainlink. In this paper, the use of hybrid chainlinks in UPP/LOW CLs is proposed for the SMPC to keep the converter losses low. However, if DC-fault blocking is a requirement, the UPP/LOW CLs may be composed entirely of FBs, although the DC fault blocking capability of the proposed converter is not investigated further in this paper.

A. Operating Principle
Although each phase-leg of the SMPC is composed of three waveshaping CLs, the operation of the converter can be more intuitively understood by considering a two-arm operation with each phase-leg divided into upper and lower arms, quite similar to a standard MMC. The two strings of IGBTs in the DS configuration (S 1 and S 2 ) switch the placement of the MID CL between upper and lower arms alternately over one fundamental cycle. This means that in the positive AC half cycle, when switches in S 1 in Fig. 1 are commanded to turn on, MID and LOW CLs constitute the lower arm while the UPP CL forms the upper arm. Alternatively, in the negative AC half cycle, the MID and UPP CLs constitute the upper arm while the LOW CL forms the lower arm. This is illustrated in Fig. 2(a) and (b).
For the case when switch S 1 in Fig. 1 is on, the voltage equations for the positive and negative poles of the DC circuit in Fig. 2(a) can be written as: To determine the basic voltage wave-shaping of the CLs, the voltage drops due to the AC side inductances and the arm inductances are ignored. Then, from an observation of (1) and (2), the following equations, relating the CL voltages to the converter AC voltage and the DC voltage, can be derived for the positive AC half cycle: Similarly, for the case when switch S 2 in Fig. 1 is turned on, the voltage equations for the positive and negative poles of the DC circuit in Fig. 2(b) can be written as: Again neglecting the voltage drop in the inductors, the following voltage equations can be derived for the negative AC half cycle: From (3), (4), (7) and (8), it can be deduced that for the positive AC half cycle, the waveshaping of the UPP CL is unique whereas the waveshaping of the MID CL and the LOW CL is not unique. Alternatively, in the negative AC half cycle, the LOW CL has a unique waveshape while the MID CL and the UPP CL have non-unique waveshapes. Therefore, due to the existence of non-unique voltage waveshapes in both halfcycles, several voltage waveshaping solutions are possible. In this paper, the waveshaping is selected to achieve symmetry in the waveforms and to avoid any sharp voltage transitions at the AC zero-crossing. Hence, the following is selected: Positive AC half-cycle: Negative AC half-cycle: Observing Fig. 2(a) and (b), it can be seen that with the proposed waveshaping of (9) and (10), the voltage appearing at the mid-point of the phase-leg is only the required AC output voltage and the voltage appearing across the phase-legs is purely DC voltage without any low-frequency distortion. The latter ensures that no additional filtering on the DC side is required.

B. CL Voltages and Currents
To derive mathematical expressions for the voltages and currents of the converter CLs, Fig. 1 is used as a reference for the converter model and it is assumed that the converter CLs are made up of a large number of cells and produce high-quality waveforms and hence, the switching effects are ignored.
Referring to Fig. 1, under ideal AC grid conditions, the voltage and current that the converter needs to generate at its AC output (converter side of the transformer) in the j-th phase (where j = 1, 2 and 3 for phases a, b and c respectively) can be expressed as: whereV c andÎ are the peak phase voltage and the peak phase current at the grid side of the transformer and r is the transformer ratio.
Since the three phases of the SMPC are connected in parallel across the DC side and assuming that the phases are balanced, the following analysis is conducted for phase a only.
Using the wave-shaping presented in (9) and (10), the voltages that need to be synthesised by the CLs can be expressed as: As will be evident in the next section, the derivation of the average powers exchanged with the CLs in steady state will make use of the Fourier series expressions of the CL voltages and currents. Hence, the Fourier series representations of the expressions in (13)-(15) are determined and are given by:

cos(nωt)
Recalling the two-arm operation of each converter phase from Fig. 2(a) and (b), the AC current will divide equally between the upper and lower arms. Also, since the phase-legs are in parallel across the DC side, one-third of the DC current flows through each phase-leg. However, since the position of the MID CL switches between upper and lower arms every half-cycle, so does the current in the MID CL. It is equal to the LOW CL current in the positive AC half-cycle and is the same as the UPP CL current in the negative AC half-cycle. Hence, the chainlink currents for phase a can be expressed as: where I dc = 3V c 2V dcÎ cos φ assuming global power balance between the AC and DC sides.
Deriving the Fourier series representation for the expression in (20), i a mid can be re-expressed as: Fig. 3 shows idealised per-unit CL voltage and CL current waveforms at unity power factor.

III. ENERGY MANAGEMENT
For the successful operation of a modular multilevel converter, the cell capacitor voltages should be stable within a pre-defined ripple margin around the nominal cell voltage. This can be achieved by ensuring that zero net energy is exchanged with the converter CLs over a period in steady-state [12]. To satisfy this condition, in addition to the global power balance between the AC and DC sides, the individual CLs/arms of the converter should also operate in power balance, meaning that the average power contributed by each CL/arm in steady state should be zero.
In this section, the internal energy balance of the SMPC is investigated by looking at the steady-state average power expressions of the CLs. In order to define the CL average powers in terms of the operating point, the time-functions of the powers of UPP, MID and LOW CLs are first computed by multiplying the voltage expressions of (16), (17) and (18) by the current expressions of (19), (22) and (21) respectively.
Extracting the DC parts of the time-functions of the CL powers and performing some arithmetic manipulation, the average powers in the CLs are given by: It can be observed from (23) and (24) that in order for the mean powers exchanged with the CLs in steady-state to be zero, the following should be true: The modulation index M of the converter is defined as the ratio of the peak converter AC output voltage to half of the DC voltage: Substituting (26) into (25), the following is derived: This shows that a "sweet-spot" exists for the converter at the specific modulation index value of π 2 ≈ 1.57 where the steadystate average power exchanged with each CL is naturally zero without further control. Theoretically, this modulation index can be set by choosing the transformer turns-ratio according to (26) for any set of AC and DC voltage levels. In practice, it may be difficult to always operate at the sweet-spot due to dynamic modulation index variations during both normal operation and faults. Therefore, active balancing of the converter's internal energy is required in the SMPC.
It can be observed from (23) and (24) that the following holds true:P a mid = − P a upp +P a low (28) (28) shows that the average powers of UPP and LOW CLs combined are equal and opposite to the average power of the MID CL. This means that when moving away from the sweetspot, according to (23) and (24), there will be a surplus of average power in the MID CL and an equal deficit in UPP/LOW CLs combined, or vice-versa. To restore the equilibrium position of zero average power in all CLs, it is necessary to implement a method for continually transferring energy between the MID CL and UPP/LOW CLs in either direction as needed. Before devising such a mechanism, the following two limitations in the SMPC are identified: r Observing the CL current expressions in (19) and (22), it can be noticed that i a upp /i a low only have DC and fundamental frequency components whereas i a mid has DC and even harmonic components. This means that there are no common frequency components between i a upp /i a low and i a mid and hence energy cannot be continually transferred between the CLs just by adding voltage correction terms to the CL voltages.
r The MID CL switches between the upper and lower arms each half cycle, and hence any balancing voltage components added in v a mid will not cancel on the AC side. That leaves only v a low and v a upp as possible degrees of freedom to transfer energy between the CLs. In light of these limitations, the method proposed to tackle the problem of energy management is to add a control variable common to all CLs of a phase-leg that can be injected just by acting on the UPP/LOW CL voltages. The formulation of this method is now described.
From (16) and (18), it can be observed that the second harmonic components in the CL voltage expressions are: And the following relationship holds: By comparing (31) and (28), it can be deduced that a common second harmonic (2ω) current through all CLs in a phase-leg would successfully achieve the desired effect of transferring energy between UPP/LOW and MID CLs. This circulating 2ω current is driven by adding 2ω components with the same polarity in UPP and LOW CL voltages only, as shown in Fig. 4. Hence, by appropriately setting the amount of 2ω current injection, the average powers of the CLs can be driven to zero in steady-state.
Since the added 2ω current components form a balanced 3-phase set in a balanced network, they do not appear on either of the DC or AC sides. Also note that although other even harmonics could theoretically be used for transferring energy, the harmonic voltage amplitudes are very small (due to the "n 2 " in the denominator of (16) and 18) and large currents would be required. Therefore, only the 2 nd harmonic is used.
To minimise its amplitude, the 2ω current injected should be in phase with the 2ω components in the CL voltages shown in (29) and (30). It is defined as: The compensating 2ω average power terms resulting from the interaction of the inherent 2ω voltage components of the CLs (29) and (30) and i a 2ω are determined as: The final average power expressions of the CLs, after the energy management action, can be written as: (35) and (36) can be equated to zero to develop an expression for k 2ω , which is the 2ω balancing current amplitude: Expressing the turns-ratio r in terms of the modulation index M using (26), (37) can be re-written as: It is obvious from (38) that if M = M ss = π 2 , then k 2ω = 0, verifying that no balancing second harmonic is required at the "sweet-spot". Moreover, the amount of balancing second harmonic required depends on how far away M is from M ss and the P-Q operating point. Fig. 5 shows idealised per-unit CL voltage and CL current waveforms after energy management for an arbitrary M = 0.83M ss at unity power factor. The effect of the balancing second harmonic on the waveshapes can be observed.

IV. SELECTION OF THE NOMINAL MODULATION INDEX
Although the "sweet-spot" may seem the obvious choice for the nominal modulation index due to the natural energy balance occurring at that value, it can be shown that the optimum value for the nominal modulation index is where the energy deviations of the CLs of the SMPC minimise. In Fig. 6, a plot of the worstcase peak-to-peak energy deviation of both UPP/LOW CLs and MID CLs against modulation index for the system ratings of an MMC HVDC demonstrator scaled down to medium-voltage   level, described in [22] and given in Table I, is shown. Based on this result, the ideal value for nominal modulation index is 1.35 to achieve the lowest possible energy storage.
Since it is proposed that the UPP/LOW CLs of the SMPC are formed of hybrid CLs (H-CLs), the matter of capacitor voltage balancing with both HB cells and FB cells present in the same CL is now addressed. For H-CLs to operate successfully, the steady-state average energies of both types of SMs should be constant from one cycle to the next. For HBs, this can usually be ensured if the current through the H-CL is bi-directional. However, since only FBs can be utilised in the negative voltage period, their energy content may see either only a sharp increase or a sharp decrease if there is no change in the current sign during that period which applies in the case of the UPP/LOW CLs, as can be seen from Fig. 5. This means that in some operating conditions, the sorting mechanism may not be able to balance the energy of the FBs.
Hence, a FB "balanceability" analysis is conducted that investigates whether the energy lost/gained by the FBs in the negative  can vary Therefore, the energy of the FBs may not be balanceable for some operating points with the absence of Q being the worst-case scenario. To conduct this analysis, the idealised FB instantaneous function is approximated as shown in Fig. 8 assuming that within the positive voltage region, the sorting algorithm will naturally ensure maximum usage of FBs in Regions B,C,D and E to balance their energy and minimum usage elsewhere. The regions within the positive voltage region that are outside of B,C,D and E are ignored in the calculation of E E net F B is calculated for a sweep of the P-Q operating region and shown in Fig. 9(a). A positive E net F B implies that the region is balanceable whereas a negative E net F B means it is un-balanceable.  The E net F B = 0 contours are then extracted and shown on a P-Q plot in Fig. 9(b). These contours can be taken as lines of demarcation between the balanceable and un-balanceable regions. It can be observed that for M = 1.35, operation at P rated with unity power factor lies in the un-balanceable region but with the addition of rated Q, it becomes possible to balance the FBs which validates the hypothesis about the absence of Q being the worst-case scenario for FB balanceability. To improve the FB balanceability over the complete P-Q region, one option is to use more FBs than that dictated by the negative voltage level which is not desirable due to additional losses. Another option is to vary the modulation index while keeping the same split between the HBs and FBs to observe the impact on FB balanceability.
Thus, the minimum value of the E net F B function is extracted for every incremental step of the modulation index. On the resulting plot, the point where min(E net F B ) crosses zero is the point of critical balanceability (PoCB). The result is presented in Fig. 10, where it can be observed that the PoCB occurs at M = 0.79M ss ≈ 1.24, below which voltages of both the HB and FB cells will balance for the complete P-Q region.
To guarantee operation within a ±10% modulation index range, the nominal modulation index of the SMPC is selected as 1.13. Note that if only FBs are used in the UPP/LOW CLs, the nominal modulation index value of 1.35 will hold.

A. Benchmarking With the MMC
A detailed comparative study between the SMPC and the standard half-bridge MMC is conducted to first establish a benchmark that facilitates further comparison with other existing topologies. The system ratings of Table I are used for this study. The rated active and reactive power and the DC-side voltage are selected equal for the two converters. Nominal modulation index values of 0.9 and 1.13 are assumed for the MMC and the SMPC respectively that guarantee operation within a range of ±10% that is typical for HVDC converters [15]. To avoid complexity, the AC line and transformer leakage impedances are ignored in the capacitor dimensioning and loss analysis. Operation at different P-Q points is modelled by setting the amplitude and phase of the supply currents with respect to the converter terminal voltage.

1) Number of SMs:
For the selected voltage wave-shaping of the CLs in Section II-A, the MID CLs in the SMPC must be rated for the peak converter AC output voltage. For the UPP/LOW CLs, the voltage wave-shapes may be altered by the second harmonic energy management action as can be observed by comparing Figs. 3 and 5.
Hence the worst-case balancing second harmonic must be considered when calculating the number of SMs needed in the UPP/LOW CLs. The general expressions for the number of SMs per CL are In the case of UPP/LOW CLs formed using hybrid CLs, the percentage of total SMs there that must be FB cells should be enough to generate the negative voltage of the CLs. Therefore, the number of FB cells in the hybrid UPP/LOW CLs is (42) and the remaining SMs are half-bridge cells. Note that in (42), M must be taken as 1.35 based on the analysis of Section IV to ensure the energy balancing of hybrid CLs.
For the system ratings of Table I, it is computed that k wc 2ω =544.5 A within the ±10% modulation index range. Then, taking the typical 0.12 pu value for arm inductance [23] (computes to 6.6 mH), and considering that the worst-case number of SMs in the MID CL are calculated at the higher end of the modulation index range, the number of SMs per converter phase for the SMPC is In the MMC, each arm is typically rated for the full DC voltage and the number of SMs per converter phase is 2V dc /V nom . Hence, the number of SMs in the SMPC is around 13% less than that in the MMC.
2) Number of Devices/IGBTs: Both of the series strings of IGBTs in the DS configuration should be rated to block the peak converter AC voltage. Assuming that the maximum voltage applied to a single IGBT in a DS is the same as V nom , the required number of IGBTs in each series string of the DS configuration is: Hence the total IGBT count of a three-phase SMPC can be expressed as Considering again k wc 2ω and the higher end of the ±10% modulation index range around the nominal value of M = 1.13, the total IGBT count is given as The total IGBT count of a half-bridge MMC is 12V dc /V nom . Therefore, a downside of the SMPC is that it requires additional devices (around 41% extra) compared to the MMC.

3) Capacitor Sizing and Energy Storage:
The dimensioning of cell capacitors in modular multilevel converters for a given cell voltage ripple is generally based on the worst-case energy deviation of each CL. The relation can be expressed as [11] where ΔE CL is the worst-case energy deviation of the CL and ΔV is the permissible voltage ripple factor. In this analysis, the voltage ripple factor is assumed as ±10% which is the value generally used [24]. In Fig. 11, the peak-to-peak energy deviations in both the MMC arms and the SMPC CLs are shown for varying phase angle values within the rated P-Q ranges.
It is observed that the energy requirement of the SMPC is majorly concentrated in the UPP/LOW CLs. Here, the maximum peak-to-peak energy deviation (20.5 kJ) is 54% smaller than that in the MMC arms (44.9 kJ). The MID CLs have a smaller additional energy requirement (6.18 kJ) which is only around 14% of that of the MMC. Eq (47) can be used to analytically Hence for the SMPC, the capacitor sizes are 19% and 78% smaller in the UPP/LOW CLs and MID CLs respectively compared to that in the MMC Due to differences in energy distribution across the converter phases between the SMPC and the MMC, a more suitable comparison parameter is the energy storage of both converters represented as a fraction of the rated power, commonly known as the H-constant (H c ). It is given for the MMC and the SMPC as The energy storage of the SMPC is 48% smaller than that of the MMC, which is achieved at the expense of requiring 41% more IGBTs. Because the energy in modular multilevel converters is stored in the SM capacitors, the amount of total energy stored directly impacts the size and the combined volume and weight of the SM capacitors. Since the SM capacitor is the bulkiest component in an SM taking up over 50% of the size and 80% of the weight [25], a given reduction in the footprint and weight associated with a smaller energy storage can be 2-3 times the increase in the same resulting from additional semiconductor devices. Thus, an SMPC converter has the potential to be more compact and lighter than an MMC converter. This may be advantageous for HVDC systems in offshore applications, where the compactness of the converter can considerably reduce the platform costs and a smaller weight of the converter can lower the cost of transporting it to the offshore site.

4) Semiconductor Losses:
The conduction and switching losses of the SMPC and the MMC are estimated by applying analytical methods described in [26]. The UPP/LOW CLs of the SMPC are considered to be formed of hybrid CLs and the ratio between the full-bridge SMs and half-bridge SMs is computed using (40) and (42). As the SMs have been rated for a nominal voltage of 1.5 kV, the 3.3 kV, 1.2kA IGBT modules (Mitsubishi CM1200HC-66H [27]) have been chosen. For a fair comparison, the same switching devices and a switching frequency of 1 kHz have been used for both converters.
In Fig. 12, the power losses in the SMPC and the MMC are plotted for their nominal modulation indices over a range of P-Q points. The losses are comparable between the two converters at unity power factor operation, however at the corner points of the P-Q region, the SMPC is between 5-10% less efficient than the MMC.

B. Symbolic Comparison With Other Existing Topologies
Other hybrid topologies of interest for comparison with the proposed converter are the AAC, EO-AAC, PH-MMC and the SBC since all of them are claimed to be more compact than the MMC. Considering the MMC as the base case and using data from other works found in the literature that present similar comparisons with the MMC, a symbolic comparative evaluation of the SMPC against the aforementioned topologies is presented in Table II. The DC voltage and AC power are considered same for all converters and the respective nominal modulation indices of the converters are assumed. N is defined as the number of submodules in one arm of the MMC and the same nominal cell voltage is assumed for all converters. Note that the references consulted do not consider a ±10% modulation index range around their nominal values, and the same approach has been adopted for the SMPC for a fair comparison. Hence, the values are calculated for the nominal M=1.13 without the ±10% dynamic range using the same methodology as in Section V-A.
In case of the AAC, while factoring in the energy stored in the DC-side filter, the energy storage is nearly 20% smaller than the SMPC which comes at the expense of 15% more IGBTs. Moreover, the DC-side filter is an additional apparatus that must be installed separately from the main valves and may lead to an increased converter footprint. EO-AAC removes the DC bus filter and the constraint on the modulation index that exist in the AAC. When compared to the SMPC, the EO-AAC has a similar energy storage but at the cost of 42% higher IGBT count. A drawback of both the AAC and the EO-AAC is the loss penalty which is due to the added functionality of DC fault blocking. However, since the application under discussion is offshore wind converters where virtually all existing HVDC installations use DC cables to transport power to the mainland, and noting that cable faults are "permanent" with no fault ride-through requirements, DC fault blocking is not a critical feature. Therefore, the SMPC can be a preferred choice over the AAC type converters in offshore HVDC applications due to comparatively better efficiency. For applications where space is at a premium, the PH-MMC and the SBC are also promising due to their compactness. When compared with the SMPC, both the converters have a smaller energy storage (around 38% and 48% smaller for the PH-MMC and SBC respectively). However, both the converters also require DC-side filtering and in addition, have higher losses (nearly 26% and 11% higher for the PH-MMC and the SBC respectively compared to the SMPC) despite the absence of DC-fault tolerance due to the high conduction losses of the H-bridge legs. Moreover, the inherent coupling between the AC-and DC-side voltages in the PH-MMC and the SBC makes AC fault ride-through difficult to achieve [30]. In contrast, since the SMPC has parallel-connected phase legs and attributes that are similar to the MMC, despite the topic not addressed in this paper, a relatively better AC fault performance compared to the PH-MMC and the SBC can be expected. Overall, it can be shown that the SMPC is a promising candidate for use in space-constrained applications with no additional filtering requirements and competes well with other compact converter topologies.

VI. CONTROL SCHEME
For devising the control scheme, the converter is assumed to be connected to a three-phase grid on the AC side and a resistive load on the DC side to keep the same configuration as the experimental setup of Section VIII. The power demanded by the DC load is fixed as the converter is expected to source a constant DC voltage on the load. Therefore, the AC power of each phase is controlled to maintain global power balance.
A block diagram of the overall control scheme is presented in Fig. 13. In addition to the standard current/voltage control on the AC and DC sides, the energy management analysis of Section III should also be incorporated in the control design of the SMPC. The energy control is implemented separately for each phase-leg. It is sub-divided into three control loops i.e the Total Energy Control (TEC), that regulates the total per-phase average energy, the Inter-Arm Energy Control (IAEC), that controls the energy transfer between MID CL and UPP/LOW CLs in each converter phase-leg, and the Inter-Chainlink Energy Control (ICEC), that regulates the individual UPP and LOW CL energies at their desired set-points. Before the ultimate step of CLs waveshaping implementation, two control outputs together determine the modulation reference signal, that are referred to as (1) the "AC part" of the modulation reference and (2) the "DC part" of the modulation reference. The "AC part" of the modulation reference comes from the AC current control, which uses the output of the TEC (the per-phase AC power reference), along with the reactive power reference, to set the AC current demand. The "DC part" of the modulation reference is obtained from the circulating current control. The IAEC and the ICEC control loops achieve the correct energy distribution amongst the CLs of each phase-leg by modifying the circulating current references.

VII. SIMULATION RESULTS
A switching simulation model of the proposed converter is developed in PLECS for medium-voltage ratings of Table I. The converter is connected to a three-phase grid on the AC side and to a DC source on the DC side and the control scheme of Fig. 13 is adapted accordingly. The main objectives of the simulation are to verify the steady-state operation and the dynamic response of the converter to changes in P-Q set-points, and additionally, to demonstrate the energy balance in the hybrid CLs when the nominal modulation index is selected according to the discussion in Section IV. The model parameters are given in Table III.  TABLE III  SIMULATION  The steady-state results are shown in Fig. 14 for rectifying active power of 20 MW and inductive reactive power of 8 MVAr. It can be verified that the proposed CL waveshaping results in the correct operation of the converter. Moreover, the sharing of the MID CL alternately between the upper and lower arms every half cycle can be observed. The DC current is free from any lower order harmonics verifying the absence of any filtering requirements on the DC side. The SM capacitor voltages in Fig. 15 are stable around the nominal value of 1.5 kV. As expected, the MID CL SM voltages oscillate at twice the AC fundamental frequency. For the UPP/LOW CL, the voltage balance is maintained for both the HB SMs and the FB SMs.  Periods of no change in HB SM voltages can be noticed when they are by-passed in the negative voltage region. The dynamic response of the converter to changes in P-Q setpoints is presented in Fig. 16, demonstrating the capability to operate over a wide range while maintaining the overall energy balance as well as the SM capacitor voltages of HBs and FBs in hybrid UPP/LOW CLs.

A. Experimental Setup
The experimental rig used as an SMPC converter is shown in Fig. 17. It has eight submodules in each converter phase; four half-bridge SMs in each MID CL and two full-bridge SMs in each of the UPP/LOW CLs. The switching devices used in the SMs are the Infineon IPB072N15N3 MOSFETs, rated at 150 V, 100 A, and Dynex DIM400WHS17-A000 half-bridge  IGBT modules, rated at 1700 V, 400 A, are used for the director switches. The AC side is connected to a three-phase programmable power source (Chroma 61511) through phase inductors, the transformer is omitted for cost reasons and a resistive load is connected on the DC side.
Due to a generic design of the experimental rig for testing various different multilevel converters, some limitations exist on the choice of specifications for the SMPC. The submodule capacitor value is larger than what is required for the given voltage ripple of ±10% (0.2 mF for MID CLs, 1.2 mF for UPP/LOW CLs). Moreover, for an adequate distribution of the available half-bridge and full-bridge SMs, the UPP/LOW CLs are formed entirely with FBs.
To demonstrate the effectiveness of the internal energy management strategy discussed in Section III, the experimental SMPC is operated away from the sweet-spot. Hence, an arbitrary modulation index M = 0.83M ss = 1.3 is selected. The system specifications are listed in Table IV. To implement the control strategies, a primary-secondary control structure using micro-controller units (MCUs) is employed. The secondary controllers (Texas Instruments F28377S) monitor all the SM voltages locally in each phase and only communicate the sum of the UPP, MID and LOW CL voltages to the primary controller (Texas Instruments F28379D). The primary controller implements the control algorithms using information from the secondary controllers and from the AC current/voltage and arm current sensors, and defines the modulation references for the converter CLs. These references are then sent to the secondary controllers. The phase-disposition PWM (PD-PWM) method explained in [8] and the sorting algorithm for capacitor voltage balancing discussed in [31] are used to generate the switching signals.

B. Experimental Results
Results from the experiment are presented to validate the operation of the converter and the developed control scheme for steady-state operation. The data has been recorded using two oscilloscopes, namely the Tektronix MSO4054 with a 500 MHz bandwidth and the Tektronix MSO3014 with a 100 MHz bandwidth. Both the oscilloscopes have a sample rate of 2.5 GS/s. In addition, the SM voltages and the CL energy transients are acquired via the primary MCU at 2 kHz sampling frequency.
The experimental results for steady-state operation are obtained for the SMPC operating as a rectifier delivering 1.5 kW on the DC load and exchanging an inductive reactive power of 600 VAr with the AC source. Figs. 18 and 19 show the results.
The three-phase converter AC output voltages (with respect to the AC grid neutral) and AC side currents, DC voltage and DC current are shown in Fig. 18. In Fig. 19, the voltages and currents of the UPP/LOW CLs and the MID CLs and the SM voltages for Phase A are presented. Fig. 19 verifies the correct implementation of the theoretical CL voltage waveshaping discussed earlier.
The MID CL voltages are full-wave rectification of the converter AC voltages and the UPP CL voltages are inverted half-wave rectification of the converter AC voltages with an offset of V dc 2 . The LOW CL voltages have a similar wave profile as the UPP CL voltages, except with the difference of a phase-shift of π. These voltage profiles are in accordance with the waveshaping discussion of Section II-A.  Fig. 19 also validates the two-arm operating principle of the SMPC in which the MID CL switches between upper and lower arms every half cycle. In the figure, during the positive half cycle, the MID CL current equals the LOW CL current while in the negative half cycle, it is the same as the UPP CL current. This behaviour is in accordance with the converter operation discussed in Section II-A.
Since the converter is operated away from the 'sweet-spot' at M = 0.83M ss , the second harmonic is injected in the circulating current for energy balancing as discussed in Section III. The effect of the second harmonic on the CL currents is visible in Fig. 19. Furthermore, as expected under balanced AC grid conditions, the second harmonic components in the phase legs of the converter cancel on the DC side as it can be seen that there are no low frequency components present in the DC side current shown in Fig. 18. The SM voltages of Phase A in Fig. 19 are also well balanced around the nominal value of 50 V, verifying that the internal energy balance of the converter is successfully maintained by the controllers.

IX. CONCLUSION
This article has presented a Switched Mid-Point modular multilevel Converter (SMPC) comprising of director switches and three chain-links of submodules in each phase-leg. Using the director switches, the middle chainlink submodules are alternated between the upper and lower arms every AC half cycle. A "sweet-spot" modulation index value of π 2 is derived at which the internal energy of the converter is naturally balanced. This equilibrium is disturbed when the converter is operated away from the "sweet-spot," in which case, the internal energy balance is restored by injecting a controlled second harmonic component in the circulating current. This also releases the constraints on the nominal modulation index which can be optimised to provide low energy storage and ensure the energy balancing of hybrid chain-links.
Whilst maintaining similar efficiency, the energy storage of the proposed converter is shown to nearly half of that of the MMC. This can potentially result in a more compact converter which is attractive for space-constrained applications such as offshore platforms. Moreover, the voltage wave-shaping of the SMPC arms is such that the two-arm operation of the MMC is preserved and hence, unlike other hybrid multilevel topologies, large DC-side filters are not required in the SMPC. These benefits are however obtained at the expense of an increase in the number of semiconductors required compared to the MMC, due to the director switches. Simulation results for medium-voltage ratings and experimental results for steady-state operation obtained using a low-power modular multilevel laboratory prototype have been shown to verify the correctness of the converter operation.