Advanced Modulations for a Current-Fed Isolated DC–DC Converter With Wide-Voltage-Operating Ranges

An active-bridge-active-clamp (ABAC) topology with its associated switching patterns and modulation techniques is introduced in this paper. The topology has been designed to comply with stringent power quality requirements in a More Electric Aircraft application. The dual transformer secondary structure of the ABAC allows the definition of a particular phase shift-based switching pattern. The proposed switching pattern ensures not only the output current switching harmonics elimination but also even power sharing between the secondary half-bridges. Consequently, passives on the low-voltage side of the converter are minimized, and transformer dc bias is eliminated. All these features can be achieved independently from the operating point of the converter. In this paper, the basic operation of the ABAC converter is first introduced. The theoretical analysis of switching harmonics elimination and power sharing is then carried out in the development of the proposed switching patterns. The theoretical claims are validated by both simulation and experimental results on a 10-kW 270-V/28-V ABAC converter.

for this application. In [11], a soft switched current-fed bidirectional half-bridge DC-DC converter was proposed where an inductor was connected between the half bridge and the LV side DC source. Taking advantage of the current-fed structure, this topology can provide smaller LV side current ripple than a DAB. Additionally, authors in [12]- [15] investigated an interleaved current-fed topology derived from [11]. In this circuit, two inductors are connected between the full bridge and the LV source resulting in an improved LV side current ripple cancellation. However, a DC voltage may appear across the high frequency transformer due to the non-ideal behavior of the semiconductors. This will cause flux biasing in the transformer core, moving the core toward saturation. Therefore, a semi-DAB topology was proposed in [16] with a split capacitor structure. In this case, DC transformer bias can be naturally suppressed without applying extra controls [17], [18]. Nevertheless, the semi-DAB cannot provide bidirectional power flow. In [19], a topology with improved power transfer efficiency and no clamp capacitors is proposed. The main drawback of this topology is that bidirectional power flow is also not achievable. The Active-Bridge-Active-Clamp (ABAC) converter was first proposed in [20], replacing diodes in the semi-DAB [16] with semiconductor switches and adopting a standard single secondary transformer structure. However, when high power applications are considered, the high current on the LV side requires paralleling of semiconductor devices. Alternatively, an increased number of transformer secondary can reduce the current stress in each switch. Therefore, when the ABAC converter is used for high power applications, a dual transformer secondary structure is considered. This configuration will not increase the number of active devices and will provide additional degrees of freedom for modulation and control.
Several modulation techniques are applicable to the ABAC converter and they can be divided into two main categories: Pulse Width Modulation (PWM) and Phase Shift Modulation (PSM) techniques. PWM techniques are mainly considered for current-fed topologies [12]- [14]. With PWM techniques, the phase shifts between secondary half bridges are fixed at 180 degree, and duty cycles of the secondary switches are utilized to control voltages on the clamp capacitors. In fact, high efficiency can be achieved with this approach, thanks to Zero Voltage Switching (ZVS) over wide operating ranges [15]. However, it presents large LV current ripple when voltages vary far from their nominal values [21]. Alternatively, PSM techniques may be considered for the ABAC converter. In fact, the ABAC converter can be directly driven with Single-Phase-Shift (SPS) modulation [20]. However, SPS cannot maintain high efficiency when voltages differ from their nominal values. In order to overcome this limitation, other advanced modulation techniques can be implemented such as Triangular Modulation (TRM) [22], Trapezoidal modulation (TZM) [23], Extended Phase Shift (EPS) modulation, Dual Phase Shift (DPS) modulation and Triple Phase Shift (TPS) modulation [24].
However, in the ABAC converter, the interleaving and load sharing of the LV output currents are adversely affected by these techniques in their classical implementation [25].
In this paper, a solution is proposed to address the aforementioned PSM limitation in current-fed DC/DC converter topologies.
A modified switching pattern is developed. It draws on the additional degree of freedom given by the ABAC converter dual transformer secondary structure. The proposed switching pattern enables the use of PSM techniques in the ABAC converter whilst maintaining switching harmonics elimination and even power sharing without transformer DC bias. The suggested methodology is supported by theoretical analysis and validated through a combination of simulation and experimental results.
The paper is organized as follows: in Section II, the ABAC topology with dual transformer secondary structure is described, and basic operation is discussed. In Section III, the issues of LV current ripple cancellation, uneven power sharing and transformer DC bias in the ABAC converter are analyzed when the converter is modulated with advanced phase shift schemes. Exploiting the dual secondary structure, a switching pattern is proposed that overcomes the limitations above and enables advanced modulation schemes that are particularly important to increase light load efficiency and to operate the converter over a wide voltage range.
The proposed pattern is general and applicable to all the modulation schemes. However, for the sake of brevity, implementation details are discussed only for TRM and DPS modulations. Simulation and experimental results are presented for a 10-kW 270V/28V ABAC, shown in Section IV and Section V respectively.

II. BASIC OPERATION
The ABAC topology is shown in Figure 1, where a full bridge on the HV side generates the high frequency primary voltage vac1.
On the LV side of the converter, two interleaved half bridge active clamp circuits are connected to each of the two transformer secondaries through power transfer inductors Ls. The two sets of secondary clamp circuits are able to operate independently, with two differential voltages, vac2 and vac3 respectively. However, the condition vac2=vac3 is imposed to achieve even current sharing between two secondary ports. Lo are the output inductors and Co is the output filter capacitor. Rs and RL are the parasitic resistances associated with the power transfer and the output inductors. The clamp capacitors C1-C4 are designed for a specific clamp voltage ripple. In general, the converter could operate with high ripple on the clamp capacitors. However, lower clamp capacitor values may impact the system controllability and the output current interleaving.  Single Phase Shift modulation (SPS) [20] can be directly applied to the ABAC converter. Using this modulation, 50% duty cycle waveforms are generated on each side of the transformer while power transfer is controlled by the phase shift angle φ. To generate theses waveforms, the HV H-Bridge (T1-T4) is switched across its active states without applying zero states. Similarly, on the LV converter side, half bridges (T5, T6) and (T7, T8) are complementarily switched, synchronously with (T9, T10) and (T11, T12), respectively. The typical waveforms obtained with SPS modulation are shown in Figure 2. The output currents iL1-iL4 are controlled by the states of the LV switches T5-T12. In each of the LV legs, if the upper switch is turned on, the correspondent output current increases, since the clamp voltages vc1-vc4 are higher than the load voltage VLV. For the same reason, if the lower switch is on, the output current decreases. When considering ideal output inductors of the same value, complete interleaving can be achieved between iL1 and iL2, as well as between iL3 and iL4, resulting in a current ILV without switching harmonics. However, the SPS modulation scheme causes considerable transformer and switching losses when operating at non-nominal voltages [26]. In fact, when variations of VHV and VLV are taken into account, soft switching constraints may not be satisfied [27].
In order to avoid these issues, alternatives such as TRM, TZM, EPS, DPS and TPS are available in literatures [23], [24], [28]. A common feature of these modulations is the need for zero voltage states applied on one or both transformer ports. As depicted in δ. There are two basic methods to generate this zero voltage state. The first is to fix the phase shift between bridges and change the duty cycle of the switches [29]. The second option is to fix the duty cycle of switches and change the phase shift [30]. No matter which approach is used, the steady state current ripples in iL1-iL4 will only be a function of the difference between the clamp voltage and the LV side voltage, i.e. the transformer primary port voltage does not have an impact on the ripple of output currents.
Moreover, the secondary voltages vac2/vac3 are related to the clamp circuits voltages, affecting the output currents ripple. For such reasons, only transformer secondary voltages are investigated in the following analysis. In Figure 3, the classical switching pattern (synchronously switched secondaries) is used where the same phase shift pattern is applied to both secondaries. The conceptual waveforms illustrate how iL2 and iL4 loses the 180 degree phase shift, and how LV currents (iL1-iL4) harmonics elimination is compromised using the classical switching pattern. Thus, TRM and DPS generate current harmonics which cause high ripple in VLV and may also excite resonances in presence of long cables [9]. For these reasons, complete LV current ripple cancelation is desired among iL1-iL4, and a different switching pattern has to be identified in order to enable the implementation of advanced modulations schemes in the ABAC without affecting the LV side power quality. Figure 3: Waveforms of the ABAC converter using (a) TRM (b) DPS with the classical switching pattern (synchronously switched secondaries).

III. THE PROPOSED SWITCHING PATTERN
The proposed switching pattern enables the implementation of advanced modulations on the ABAC converter by taking advantage of the dual transformer secondary structure. The analysis is developed for switching patterns that are applicable to any phase shifted modulation scheme (TZM, TRM, EPS, DPS and TPS). For the sake of brevity, only TRM and DPS have been discussed in this paper. However, a similar approach can be applied to any other similar modulation scheme.

A. Switching frequency harmonics elimination
There are two ways of restoring the interleaving of the output currents iL1-iL4. In both cases, the voltages vac2 and vac3 will not be affected, thus maintaining the same transformer currents and the same power transfer. When compared to Figure 2, the driving signals for the half bridges (T9, T10) in Figure 4 (a) are shifted forward by an angle δ, and gate drivers of the half bridges (T11, T12) are shifted backward by the same amount (pattern I). Alternatively, in Figure 4 (b), gate drivers of half bridges (T5, T6) are shifted forward by an angle δ and gate drivers of half bridges (T7, T8) are shifted backward by the same amount (pattern II). In both examples, complete current ripple cancellation is always achieved, reestablishing interleaving. It is important to highlight that although two secondaries are shifted in different manners, the constraint vac2=vac3 is always satisfied, allowing even power sharing between the two secondary ports. The output current ripple is determined only by the clamping voltages, the LV side voltage and the switching pattern, regardless of the transformer voltages. In steady state, the average clamp capacitor voltage is always equal to twice the LV voltage, since the duty cycle is fixed at 50% and the clamp circuits behave as a classical boost converter.. Therefore, as shown in Figure 4, taking iL2 as an example, when T7 is on (G7=1), iL2 increases driven by a voltage with a value of VLV, and when T7 is off (G7=0), iL2 decreases driven by a voltage with a value of -VLV . The reason why iL2 changes in (a) and (b) is that different switching patterns are used in two cases for the clamp circuits, thus changing the instantaneous iL2 current waveforms.
However, the fact that the clamps decouple the output inductors current waveforms from the transformer voltages, thus keeping vac2 the same in both switching patterns, is one of the merits of such switching patterns. Figure 4: TRM for the ABAC converter with the proposed switching patterns: (a) "pattern I" and (b) "pattern II".

B. Analysis of uneven power sharing
Although power can be evenly shared between the two secondary ports if vac2=vac3 holds true when the switching patterns in Figure 4 are applied to the ABAC converter, uneven power sharing between two bridges in the same secondary is still possible.
This leads to unequal average output currents (iL1-iL4) and transformer currents (is1, is2) DC bias. As an example, consider the case where "pattern I" is applied with the converter operating in buck mode (i.e. power flowing from HV side to LV side). This is shown in Figure 5, where vac1/N is the transformer primary voltage reflected to the secondary. In this case, C3 can only be charged or discharged when T9 is on, while C4 can only be charged or discharged when T11 is on. In order to explain the uneven power sharing and its consequences, a hypothetical steady state condition is considered. In particular, C3 is considered equally charged and discharged in each switching cycle. This indicates that the voltage variationΔvc3 over one switching cycle equals zero. The AC component of the transformer current is2 is denoted as is2ac. Ideally, zero DC bias on transformer current is assumed, therefore, is2=is2ac. The expression for voltage variationΔvc3 is expressed as where IL3 is the DC component of output inductor current iL3, Ts is the switching period and Qa is the area of the triangular current waveform is2, highlighted in green in Figure 5 (a). Qa represents the electrical charge flowing into the clamp capacitor C3 when G9 is on.. Therefore, Qa can be calculated as where, as shown in Figure 5. DC components of the output currents iL3 and iL4 are expressed as If balanced output currents are assumed, i.e. 3 4 the voltage variation Δvc4 on capacitor C4 can be derived as follows where Qc, highlighted green in Figure 5 (b), represents the electrical charge flowing into C4 when G11 is on but G9 is off. Similarly to Qa, Qc is defined as and Qb is defined as the integral of the transformer current is2ac when G9 and G11 overlap. Qb is also highlighted in grey in Figure   5 (b).
Substituting (1)-(4) and (7), (8) into (5), the following expression of voltage variation across C4 can be derived This means that with symmetrical transformer secondary current is2 and balanced output currents IL3=IL4, a steady state condition for both capacitor voltages is not achievable. Therefore, a DC offset is2dc on is2 and a deviation ΔIL between IL3 and IL4 have to be imposed in order to drive the clamp voltage variation to zero in steady state condition. This leads to uneven power sharing between the two half-bridges in each secondary. A more detailed quantitative analysis will be provided in the next subsection. Furthermore, equation (9) indicates that uneven power sharing between the two half bridges always exists if Qb is not equal to zero. Using "pattern II" will lead to the same waveforms and equations where the role of C3 and C4 is inverted. The same analysis is applicable to other modulations requiring zero states on the secondary side, such as TZM, EPS and DPS.

C. Criteria for even power sharing
Analytical formulas of both transformer DC bias (is2dc) and deviation between IL3 and IL4 (ΔIL=IL3-IL4) are discussed in this subsection in order to derive a criteria for even power sharing. To begin with, the first equation describing the relationship between is2dc and ΔIL is derived in steady state, assuming negligible ripple in the clamp voltages. The transformer DC bias can be expressed as: Where ds is the duty cycle, which is kept constant at 0.5. Vc3 and Vc4 are steady state voltages across the clamp capacitors C3 and C4. Considering the fixed duty cycle operation, in steady state Vc3 and Vc4 can be represented as: Substituting (10) into (9), the relationship between is2dc and ΔIL can be derived: A second equation between is2dc and ΔIL can be derived following the analysis in [31]. When only the AC component of transformer current is considered, the average currents flowing from the power transfer inductor Ls into the clamp capacitors C3 and C4 are defined as: where fs is the switching frequency.
From (13), the relationship between is2dc and ΔIL can be derived: Substituting (12) and (14) into (11), the analytical forms for both is2dc and ΔIL are obtained as in (15). It is important to note that equation (15) is true for all modulations when "pattern I" or "pattern II" is used.
According to (15), the only way to ensure even power sharing without neither DC offset on the transformer current nor deviation between output inductor currents is to impose Qb equal to zero. In other words, when G9 and G11 overlap, the integral of the transformer current AC component has to be equal to be zero.

D. The proposed approach
As discussed in the previous subsections, the two switching patterns ("pattern I" and "pattern II") are both able to produce complete interleaved output currents but result in unequal DC output currents (IL1-IL4) and transformer currents (is1, is2) DC bias.
Based on (15), when G9 and G11 overlap, the integral of is2ac has to be equal to zero in order to achieve even power sharing.
Consequently, considering that "pattern I" and "pattern II" have opposite effect on C3 and C4, a combination of these two patterns, illustrated in Figure 6, is proposed in order to overcome this issue by applying "pattern I" and "pattern II" alternatively every other switching period. In the proposed approach, Qb for both patterns can be written as: Qb_I and Qb_II are different from zero, however their sum does, as shown in (18).
Therefore, the proposed approach can guarantee even power sharing in two switching cycles. The same concept also applies to C1 and C2. It is important to highlight that, as shown in Figure 6, although both switching patterns are used, the switching frequency remains to fs. Moreover, the duty cycle of all switches has an average value, in two switching cycles, equal to 50%. Thus, a fixed voltage ratio in steady state between the voltage VLV and the clamp voltages (vc1-vc4) can still be achieved.
The practical implementation of the proposed switching pattern requires the generation of a variable phase for each driving signal between two adjacent switching periods. In particular, a phase shift φ is generated to impose a phase shift between vac1 and vac2-vac3 while a phase shift δ is used to generate zero voltage states on vac2-vac3. This could be implemented in FPGA, but a more cost-effective implementation could be to use commercial microcontrollers with embedded EPWM modules. In particular, a Texas Instruments C2000 is considered in this analysis. The proposed implementation is shown in Figure 7, where counters for each EPWM module are independently driven and compared with a fixed value, equal to 50% of the counters maximum value, Cmax.
EPWM1 is employed solely for generating the phase updating signal in this paper, which corresponds to the instant when its counter reaches Cmax, while EPWM2-EPWM7 are responsible for generating the driving signals for the switches G1-G12, respectively. However, it is also possible to generate the driving signals G1-G12 with EPWM1-EPWM6, and to change CMPB of EPWM1 accordingly, to trigger the ADC sampling, phase synchronization and control interrupt. However, the implementation approach in this paper tries to deliver a more intuitive explanation of the proposed phase shift method by having a separate updating signal.
Only the gates of the upper switches in each half bridge are shown in Figure 7, since each leg is complementarily switched. The red dashed lines in Figure 7 represent the boundary between the two switching pattern, which correspond to the falling edge of vac3 where the Phase Shift update must take place. Since vac1 is in phase with EPWM2, the phase shift α between EPWM1 and EPWM2 can be calculated as     (19) where δ stands for the duration of the zero voltage level in vac1 and vac3. φ represents the phase shift angle between vac1 and vac3.
While phase shifts of EPWM3-EPWM7 with respect to EPWM2 are determined by the specific modulation used, the phase shift angle α between EPWM1 and EPWM2-EPWM7 is referred as in (19). A positive α stands for a phase delay of EPWM2-7 with respect to EPWM1, while a negative value denotes a backward shifting of EPWM2-7. Considering the case of TRM and DPS, the counter values for each EPWM modules, loaded at the beginning of each switching period, are calculated as in Table І where θHV and θLV represent the duration of zero voltage level for vac1 and vac2-vac3, respectively. In the proposed scheme, it can be noted that EPWM4A (G5) and EPWM7A (G11) always have a phase shift of π, as for EPWM5A (G7) and EPWM6A (G9). Therefore, 180 degree phase shifts between iL1 and iL4 also iL2 and iL3 are guaranteed and complete current ripple cancellation can be achieved. The implementation approach is also valid for other modulations, such as TZM and TPS, if appropriate modifications to φ and δ are applied.

IV. SIMULATION RESULTS
The overall block diagram for simulation is shown in Figure 8 where  [30]. However, TRM and DPS perform better than the classical SPS when input and output voltage vary further from their nominal values. It is worth mentioning that only one control variable is required to achieve the desired voltage regulation. However, according to the specific modulation, several solutions can be found to achieve the desired power transfer whilst minimizing other parameters, such as transformer peak/RMS current or efficiency at light load or in nonnominal operating conditions. The common feature of all the modulation method considered in the paper is that they all receive a single control parameter from the output voltage controller and they calculate the other required parameters based on the constitutive equations of the modulation scheme. This paper focuses on the specific switching patterns applied to the ABAC converter in order to enable these modulations, and enabling them to be used generally for all other modulations techniques.
For this reason, the detailed analysis and implementation of TRM and DPS can be found in literature [22], [28], and they are not reported here for the sake of brevity.     Simulation results using SPS are provided in Figure 9, where the rated power (10kW) is transferred from the HV side to the LV side. The HV bus is set to 270V while the LV bus is regulated at the nominal value of 28V. In accordance with the analysis in Figure 2, output currents iL1-iL4 are always interleaved. Therefore, the current ripple on the output currents is well cancelled, resulting in VLV with small ripple. Simulation results in Figure 10 (a) and (b) show waveforms under low power operation using TRM with the classical switching pattern and the one proposed. It can be seen from Figure 10 (b) that LV current ripple is well cancelled using the proposed method, and the peak-to-peak LV ripple is negligible. On the other hand, with the classical switching pattern the peak-to-peak value of VLV is significantly large, due to the loss of current interleaving. Additionally, DC offset on the transformer current is2 and deviation between the DC components of output currents can be also observed in Figure 10  To validate the applicability of the proposed method to different modulations, additional results are provided for DPS. This modulation is particularly useful in applications where a reduced reactive power is desired in the light and medium power range [28]. In Figure 11 (a), "pattern I" is applied while the proposed combination of "pattern I" and "pattern II" is applied in Figure 11 (b). VHV and VLV are set to 170V and 28V while an output power of 3kW is transferred from the HV to the LV side. The LV current ripple is well cancelled, and the VLV ripple is also small in both cases. However, due to the uneven power sharing analyzed in section III, when "pattern I" only is applied, the output currents iL1 and iL2 present different DC components, and the transformer current is2 also has a DC offset. On the other hand, with the proposed method, the output currents are balanced and the transformer current is2 presents a negligible DC component.  Finally, losses for all the active devices including HV side and LV side switches are evaluated. The evaluation comprises both switching and conduction losses, considering the three modulations discussed in this paper (SPS, DPS and TRM). Losses are estimated in PLECS using losses models based on data sheet parameters. It is worth pointing out that the proposed loss comparison is solely intended as a relative evaluation of different modulation schemes and should not be considered as an accurate loss prediction fort the converter. With SPS, efficiency drops when the ABAC is operated in non-nominal voltage conditions. Therefore, operating voltage condition 170V/28V is considered here in the simulation. As shown in Figure 13, since the transformer current stress is considerably reduced using TRM and DPS [28] at light load, losses are reduced compared to SPS. Consequently, TRM presents the highest efficiency. However, due to its limited power transfer capability [32], TRM is only applicable at very low power. At higher power, DPS presents less losses than SPS, thanks to the lower transformer peak current [33]. Other modulations, such as TZM, EPS and TPS [24], can also be applied using the proposed switching pattern.

V. EXPERIMENTAL RESULTS
The proposed methodology has been validated on a 10kW, 100kHz, 270V/28V prototype, shown in Figure 14, featuring the same parameters used in the simulations and shown in Table II and III. A TMS320F2837xD evaluation board from Texas Instruments enhanced by a custom interface board has been adopted as the digital control platform. The output voltage VLV is measured and controlled by a PI controller as discussed in Figure 8. In the experimental prototype, the clamp capacitors are designed for 2% voltage ripple at full power. This conservative design has been selected in order to prioritize the implementation of advanced modulation techniques on this converter.
Experimental results are shown in Figure 15 where the ABAC is modulated with SPS to deliver a power of 10kW to the LV resistive load, which is thus regulated at the reference voltage of 28V with an applied input voltage of 270V. The primary/secondary voltages of the transformer and transformer secondary/primary currents, together with the output voltage are shown from top to bottom in Figure 15. The output voltage is well regulated with 550mV peak-to-peak ripple. This results in a loss of current interleaving when using the classical switching pattern as shown in Figure 3. To avoid the large voltage ripple shown in Figure 10(a), the output inductance in this experiment has been increased to Ls=3.3uH. It can be noted from Figure 16 that large voltage ripple affect also the control effectiveness. In fact, an error between the voltage reference (28V) and the measured mean LV voltage value (26V) is present due to the sampling of VLV. One sampling time instance, positioned according to the modulation and control implementation discussed in Figure 7, is highlighted in Figure 16 with a red dashed line.
The figure shows that VLV is sampled close to the peak and instead of regulating the mean value to 28V, a voltage close to the peak is controlled to 28V, thus resulting in a lower average value. However, when the proposed switching pattern is utilized in Figure 17, the current interleaving can be restored. It can be noted that VLV peak-to-peak ripple can be reduced to 506mV, approximately ten times lower than the ripple with the classical switching pattern (4.86V). The ripple of current iL1 and iL4 are shown in the figure. Besides, steady state control error is not present anymore with the proposed switching pattern. VLV is well regulated at the reference value of 28V. Comparisons between the proposed switching pattern and "pattern I" are carried out when DPS modulation is applied. Results are shown in Figure 18 (a) and (b) under operating condition P=3kW, VHV=170V and VLV=28V. When the proposed switching pattern is implemented, the output currents are modified to guarantee LV current ripple cancellation and a negligible transformer current DC bias is present, as shown in Figure 18 (b). On the other hand, when DPS is implemented using solely "pattern I", as illustrated in Figure 18 (a), two output currents in the same secondary have a difference of 11A in their mean value, and the transformer secondary current is2 presents a DC bias of -23.2A. This provides a further validation of equation (15).

VI. CONCLUSIONS
In this paper, the ABAC converter is introduced as a suitable power converter topology to transfer power between 270VDC and 28VDC buses in a MEA where stringent power quality requirements apply. The ABAC converter can be modulated with SPS.
However, SPS cannot keep high efficiency when input/output voltage differ from their nominal values. In order to overcome this limitation, other modulation techniques can be implemented such as TRM and DPS. However, in the ABAC converter, the interleaving and load sharing of the LV output currents are adversely effected by these techniques in their classical implementation.
This limitation can be overcome by exploiting the additional degree of freedom given by the dual transformer secondary structure proposed in this paper. This allows the definition of a modified switching pattern that enables the use of advanced modulations with the ABAC converter whilst maintaining switching harmonics elimination and even power sharing without transformer DC bias. The effectiveness of the proposed method has been verified by simulations and experiments results from a 10kW ABAC converter.