Parametric study of optimum gate-resistance for performance and short-circuit robustness of novel half-bridge IGBT modules

This paper jointly investigates the switching performance and the short-circuit (S.C) turn off behavior of a novel half-bridge (2in1) IGBT power module concept with the low stray inductance (Lσ), which has been available in the market since 2015. Since this package was designed for improving the performance of Si-based switches and is a pioneering solution for designing WBG switches through reducing the Lσ of the switch itself, investigations of S.C are an important task for both researchers and designers. The performance of a Half-bridge (2in1) Silicon N-channel IGBT has been examined with different temperatures, switching transients and testing under S.C conditions, where the extracted results offer a clear overview of S.C of Half-bridge (2in1) package and trade-offs between switch losses and short-circuit safe operating area (SCSOA), and finally prevention of false turn-on after short-circuiting due to Lσ.


I. INTRODUCTION
In searching for low stray-inductance packages capable of utilizing semiconductors at the border of their limits whilst also commercializing wide-band-gap (WBG) semiconductors, manufacturers have been developing new open standard packages for Half-bridge (2-in-1) module platforms since 2016, modules are known commercially as nHPD 2 , XHP, LinPak and SemiTrans20. Designing halfbridge (2-in-1) package by semiconductor's manufacturers is a part of the optimization of circuit design solution in preventing large overshoot and ringing in WBG devices [13]. (2-in-1) half-bridge configurations have low inductance by narrowing the gap between p-n terminals gap, arranging terminals side by side [10]. and an <30nH stray inductance thanks to low stray inductance standard busbars for (2-in-1).
half-bridge, which make this package popular for high current and high voltage applications. The package appearance and an equivalent circuit are shown in Fig. 1. Manufacturers claim that this new package provides around 30% higher power density and 75% less internal stray inductance when compared with conventional packages [1]. Experimentally, the maximum switch's loop stray inductance measured is 14.7nH shown in Fig. 3    Rail traction converters  Aerospace converters  Marine and offshore applications  Automotive  Solar converters and wind turbine converters As reliability and fail-safe operation are highly recommended for these applications, the aim of the research project is to examine mainly robustness performance of this new technology since this technology is nascent. In the late chapters we will discuss about S.C behavior of the mentioned module, then we will investigate the source for S.C oscillation and things to do to prevent turn off oscillation during S.C.

II. SHORT-CIRCUIT TURN-OFF
Samples were examined with S.C type II (The configuration has been setup for a S.C test presented in Fig.4. The pulse of high-side and low-side overlapped within 1.5us) where the S.C started from 900A.  In the case of ܴ ீିை =2.7 Ω, ܸ ீாି௪ௌௗ increases, until reaches threshold ܸ ீாି்ு , then switch involved a chain of parasitic oscillation shown Fig. 8.

BEHAVIOUR
Lower gate currents and/or higher gate resistances result in a slower voltage slope at turn-off. Thereby, the stored charge in the drift region of the IGBT is partly extracted and, thus, the ௗ ௗ௧ is increased. [6]. Switch-off transients for our DUT with different ܴ ீିை shown Fig. 9. Four types of failures in IGBT may occur during a S.C [12].
Turn-off failure can be related to an excessive power surge involved in a voltage overshoot at the device turn-off. This failure mode strongly depends on the ܴ ீ value and the collector stray inductance that governs the ௗ ௗ௧ [12]. Also, ‫ܧ‬ ‫݂݂‬ increases with increasing ܴ ீିை . shown in Fig. 10.
(Note that ‫ܧ‬ ‫݂݂‬ been measured according to: "IEC60747-9 (2007) [3]. An IGBT may survive long S.C times but fail when turned off. Thus, an IGBT rated for long S.C time may fail at the turn-off simply due to the "dynamic latching.", since the turn-off speed is to some degree dependent on the tum-off gate resistors [2].
There are two possible fast turn-on oscillations during S.C: In both the cases that are somehow related to the input capacitance ‫ܥ‬ ௦ , the ‫ܥ‬ ௦ must be charged to the threshold voltage, after which the device begins to turn on, and if discharged to the plateau voltage the device begins to turn off. Figure 10. The parasitic capacitance current path lowside IGBT during parasitic Miller capacitance switching A large voltage overshoot on ܸ ா induces a current into the Miller capacitance and raises the voltage of ܸ ீா . The parasitic capacitance current path low-side IGBT during parasitic Miller capacitance switching Shown Fig. 10. Also, when turning off the lower IGBT in a half-bridge during S.C ௗ௩ ಶ ௗ௧ occurs across the upper IGBT diode. This current will pass through the Miller capacitance and then passes through ܴ ீ . If the voltage drop reaches the threshold voltage, a false turn-on will occur.

III-I FALSE TURN-ON VIA THE MILLER CAPACITANCE
Neglecting the influence of the gate driving circuit, the gateemitter voltage can be calculated by [8].

III-II FALSE TURN-ON VIA STRAY INDUCTANCES
The effect of the Emitter inductance leads to an overshoot on the Collector current ‫ܫ‬ coinciding at the same time with the highest voltage drop at the Collector-Emitter voltage ܸ ா . The combination of high Collector current and low Collector-Emitter voltage seems to be correlated with the occurrence of Gate-voltage oscillations under the shortcircuit event [11]. The equivalent circuit of Gate Drive Loop inductance of low-side IGBT shown Fig. 12. When a large current is created by short-circuiting, turn-off will occur with large ௗ ௗ௧ . This induces a voltage equal to ‫ܮ‬ ఙ ௗ ௗ௧ in the circuit stray inductances. This voltage overshoot, if too large, would cause a chain of false switching, resulting in failure due to an excessive power surge or latching.
This mode of failure could be avoided by minimizing the circuit stray inductances on the DC side of the switching device, also called "DC loop" inductance. The objective could also be achieved by slowing the rate of fall of fault current, which again some degree is dependent on the tum-off series Gate resistor, ܴ ீିை [2] .

IV. DEALING WITH TURN-OFF OSCILLATION
From (2) we understood that to prevent parasitic Miller capacitance switching, the quotient Since -16 V is applied to ܸ ீ during turn-off: If we call the gate node on substrate ܸ ீିௌ : From (10) we can conclude that by increasing ܴ ீିை we are increasing the negative voltage applied to ܸ ீ substrate. Hence, to prevent parasitic turn-on due to ‫ߪܮ‬ after S.C we must choose a value bigger than 2.7Ω.
From (2) and (10) by adding an external ‫ܥ‬ ீா we can prevent parasitic turn-on after S.C due to stray inductance and Miller capacitance same time.
Although half-bridge IGBT modules manufacturers recommended 100Ω for ܴ ீିை , but in searching an optimized value and the minimum value, the values for ܴ ீିை during our tests have been chosen much less than this value (from 15 Ω to 2.7 Ω) to examine the limits of ܴ ீିை .
Since the ‫ܧ‬ unaffected by the temperature during our experiments, this means that turn-off oscillations happened independently of module's temperature. Turn-off transients for different temperatures are shown in Fig. 12. Note that in our samples even though the device started parasitic switching during S.C, but never involved dynamic latched up since upper thyristor never activated during the short circuit. It proves our samples were well designed in the Physical stage [7].

CONCLUSION
In this paper, half-bridge (2-in-1) IGBT modules switching performance and robustness were examined using a realistic scenario (S.C type II). The effect of ܴ ீିை on short-circuit illustrated. ܸ ீ relations during false turn-on via stray inductance has been extracted and shown that it does not depend on ‫ܮ‬ ఙିோீ . Also, it was demonstrated why with increasing the ܴ ீିை the chance of involving parasitic oscillation decreases, it was concluded it is sufficient to select ܴ ீିை higher than 2.7 Ω to prevent turn-off oscillation due to stray inductance after S.C; the value is fully compatible with optimum switching performance for half-bridge IGBT module and it doesn't need an ulterior consideration. Future work could be directed at investigating the dependency of switching frequency and S:C oscillation . Also, proposed to investigate an optimum external ‫ܥ‬ ீா to prevent parasitic turn-on after S.C as one solution for both of stray inductance and Miller capacitance.