Thermal Analysis of High Power High Voltage DC Solid State Power Controller (SSPC) for Next Generation Civil Tilt Rotor-craft

This paper explores different possible topologies of a high-power high-voltage bidirectional DC solid state power controller (SSPC) for aerospace applications. The most suitable topology is then selected for design and implementation of the SSPC. A detailed analytical thermal model of the most preferred SSPC is presented in this paper. Using the thermal model, the junction temperatures of the potential IGBT and MOSFET modules selected for the SSPC design are estimated during nominal and over-current situations. The prediction of the semiconductor device’s junction temperature is of major significance during the design process of the SSPCs to ensure thermal stability during over-current situations. Later, a thermal model of the SSPC is built in a computer simulation software named PLECS and the junction temperature of the devices are evaluated for nominal and all over-loading conditions. In addition, the overall efficiency, weight, and power density of the SSPCs with respect to the selected devices are approximated. The device that exhibits better thermal resilience and good power density is selected for the future development of the DC SSPC for more electric aircraft.


I. INTRODUCTION
The main concept behind more electric aircraft (MEA)/allelectric aircraft (AEA) is to replace non-electrical sources, transmission, and loads with the electrical ones. The new electrical architectures for MEA exhibit better efficiency, minimal weight, flexible load location, reduced volume, decreased noise/vibration, and increased reliability than that of the existing conventional architecture [1]- [4]. However, many advancements on MEA architectures are still in research and development phase.
The project INSTEP delivers a new electrical power system (EPS) for next-generation civil tilt rotorcraft (NextGen CTR). The EPS for CTR is based on new ± 270 V DC distribution system. The proposed architecture consists of three 90 kW generators and two 50 kW generators (with rectifiers) connected to ± 270 V DC bus. The DC bus acts as the main transmission system within the rotor-craft. Additional power electronic converters (PECs) along with circuit breakers are employed for interfacing different AC/DC loads and batteries.
One of the major challenges for the development of EPS is the design of suitable circuit breakers for high current and high voltage DC system. Traditional electromechanical circuit breakers (ECB) used in AC based systems offers low on-state resistance with galvanic isolation. However, these ECBs are not suitable for DC application due to its inherent arching problem and limited life. In addition, ECB is bulky and has a slower response time as compared to semiconductorbased solid-state power controllers (SSPC). The hybrid circuit breakers (HCB) makes use of both copper contact and semiconductor devices but poses design complexity [3], [5], [6]. The schematics of three different types of CBs are shown in Fig. 1. Various types of solid state based circuit breakers and recent technological advancements in this field are over-viewed in [5]- [10]. In [5], the different types of semiconductor topologies for the SSPC along with design challenges are presented. The SSPC based on SiC devices for low current applications are experimentally verified in [7]. Solid-state based circuit breakers for microgrid applications are described in [6], [8]. High-voltage and high-power based SSPC on static induction transistor (SIT) devices are demonstrated in [10].
The SSPC is a 'normal on' switch carrying current throughout its life. In addition, the breaking current of the SSPC is 8-10 times higher than the nominal current [5]. Therefore, detailed thermal analysis of the SSPC during nominal and over-current situations needs to be explored. In this paper, various possible semiconductor topologies of the SSPCs are explained. Then, suitable semiconductor devices are selected for the most preferred topology and their thermal stability are analyzed. The estimation of device junction temperature is of great importance during the design process of the SSPC. The SSPC should ensure to flow nominal current for infinite time and over-currents for different time durations without thermally damaging its components. Section II outlines various types of SSPC topologies that can be used for bidirectional DC applications. The description of the studied SSPC is presented in Section III. Device selection and analytical thermal computations of the device's junction temperature are explained in Section IV. The validations of the analytical results with PLECS simulations are reported in Sections V.  Table I. Topology-3 is the most suitable topology for NextGen CTR EPDS since it allows the use of various semiconductor devices (MOSFET/IGBT/JFET) in either single or multiple channel configurations.

III. BIDIRECTIONAL DC SSPC FOR NEXTGEN CTR
The schematic circuit for the SSPC design for NextGen CTR shown in Fig. 4 consists of voltage source, transmission impedance, SSPC, and RC load. The design specifications of the DC SSPC are mentioned below: • Nominal voltage rating: ± 270 V , ± 170x5 A (850 A for 500 ms), ± 170x2 A (340 A for 2 sec) From the design specification of the DC SSPC, the approximate I 2 t tripping curve is generated and presented in Fig.  5. The pulse current requirement of this SSPC is higher than offered by commercially available SSPCs [5].  • Being able to handle the nominal current and specified over-load currents without exceeding maximum junction temperature (T jmax ) • Min voltage stress (540 V) • Operating ambient temperature is considered to be 85 • C For this application, high current MOSFETs/IGBTs are selected with voltage rating more than 1200 V. The basic device selection criteria are mentioned below: • Minimum switch voltage (2x540 V) • Minimum on-state resistance MOSFET/JFETs are very useful for low current SSPCs and these semiconductor devices can be paralleled for achieving higher current rating. The paralleling operation eventually reduces the conduction loss and each parallel channel can be used for different loads. However, additional parallel devices ask for additional drivers and heat sinks which impact the power density of the SSPC. On the other hand, IGBTs are effective for single channel SSPC with slower response. In addition, low cost, mature technology, high voltage and current ratings with good thermal characteristics make IGBT a good choice for high power SSPC. A comprehensive comparison study of MOSFET-based SSPC and IGBT-based SSPC with topology-3 is introduced in the following section.
Three MOSFETs currently available on the market (APT100MC120JCU2-ND-Microsemi, CAS325M12HM2-CREE, and CAS300M12BM2-CREE) with low on-state resistance are selected for the design of the DC SSPC in this project. The various ratings and details of the selected devices can be found onCREE and Microsemi official websites [12]- [14]. For applications where the voltage requirement is over 600V, no silicon MOSFET/JFET are available for higher current rating. Therefore, all selected MOSFETs are silicon carbide (SiC) MOSFETs which are several times expensive than ordinary MOSFETs.
While paralleling the IGBTs, one of the parallel loop may get overheated due to improper heat dissipation. The on-state resistance of the overheated IGBT decreases which will increase the magnitude of current flowing through it. This phenomenon continues till the junction temperature of the overheated IGBT reaches its limit. Therefore, the paralleling of the IGBTs is not preferred. So, IGBTs with high current ratings are chosen for this application. Three IGBTs (CM1400HA-24-Mitsubishi, FZ900R12KP4-Infenion, and FZ1600R17HP4 B2-Infenion) are selected for this application. The specification of these three IGBTs can be found in [15]-[17].

B. Thermal analysis of semiconductor devices during steady state
A simplified thermal circuit of the semiconductor device is illustrated in Fig. 6 [18]. The junction to case thermal impedance (R thjc ) is the intrinsic parameter of the device which can not be changed with external circuit design and heat sink. However, the case to the ambient thermal impedance (R thca ) depends on the size of heat-sink and grease/paste used between the heat-sink and the case. The size/shape/material of the sink determines the physical current limit of the semiconductor device. The maximum heat loss (P max ), steady state drain current for MOSFET (I d(mos) ) and IGBT (I d(igbt) ) as the function of thermal resistance of the heat-sink are given by eqns. (1), (2), and (3) [5], [19], [20]: where T j and T a are operating junction temperatures and ambient temperature in • C, respectively. The parameters, R dson(max) and R thja is the maximum on-state resistance of the device and thermal resistance from junction to ambient, respectively.
The main parameters that determine the physical current limit of the devices are the cumulative thermal resistance from device's junction to the ambient. The different heat sinks proposed for the calculation of theoretical current limit are listed in Table II. Using the datasheets of the devices provided in previous tables and sink thermal resistance, the maximum power dissipation limit and physical drain current limit of the selected devices are calculated. The value of drain current in less than the specified maximum current limit in the datasheet. This is due to the high ambient temperature (85 • C) around the device and finite heat sink to dissipate the loss-power.
Since, the steady state current of the SSPC is higher than that of physical current limit of the devices in case of MOSFETs. There, multiple channels of the MOSFETs need to be paralleled to match the current rating. The number of channel (n) required can be expressed as [5]: After paralleling multiple MOSFET matrix, the junction temperature should not exceed the maximum junction temperature limit. The maximum junction temperature as a function of number of channels can be evaluated as [5]: For the IGBTs, the number of parallel loops can be approximated with the help of eqn. (6). However, the maximum number of channels necessary should be always less than one.
C. Thermal analysis of semiconductor devices during overcurrent situation The rated breaking current of the SSPC is more than nine times the nominal current. Therefore, during tripping of the SSPC, the junction temperature may go beyond the maximum limit and eventually destroy the device. The transient thermal junction to case impedance of the device decides the transient increase in junction temperature during pulsating current. The minimum number of parallel channels required for the MOSFETs in order to withstand the transient current is expressed in eqn. (7). The maximum junction temperature during transient condition can be calculated using eqn. (8) [19], [20].
T j(act) >= I 2 dc n 2 R dson(max) Z thjc + T c < T j(max) (8) where Z thjc and T c are the transient thermal resistance and the case temperature of the devices.
The number of parallel loops required during and maximum junction temperature of the IGBTs during transient condition can be approximated as [19], [20]: T j(act) >= I p V cesat(max) Z thjc + T c < T j(max) (10) where V cesat(max) is maximum on state voltage drop of the IGBT.
The number of MOSFET parallel loops are calculated for both steady-state and transient state. However, the higher 'n' (between steady-state and transient state) should be number of parallel loops for thermal stability. For Microsen MOSFET(APT100MC120JCU2-ND), the number of channels required to sustain very high peak current is more than 20 (as calculated using eqn. (7)) therefore, it would be very unreliable to develop SSPC with forty MOSFET devices. However, five channels are sufficient to build SSPC using high current CREE MOSFETs.
For any IGBT with a negative coefficient of resistance, the value of n should be always less than one and T j(act) should be always less than T j(max) of the device. The number of channels required and junction temperature (evaluated analytically) under various conditions for different semiconductor devices is listed in Table IV. High current CREE MOSFETs ( CAS300M12BM2/CAS325M12HM2) are the most suitable for multichannel SSPC with the easier cooling mechanism. However, device counts are higher in order to meet the peak current rating of the SSPC.
Single channel SSPC can be designed using Mitsubishi IGBT (CM1400HA-24S), however, maximum junction temperature is just within the limit during the current spike. The Infineon IGBT (FZ1600R17HP4B2) exhibits better thermal stability than any other devices but is slightly bulkier and more expensive than other IGBTs of similar ratings. The other lighter and cheaper Infineon IGBT (FZ900R12KP4) cannot be used due to thermal instability during over-current operation and is not further included in the simulation.

V. THERMAL SIMULATION OF THE SSPCS
In order to validate the thermal stability of the SSPC, the thermal circuit of the SSPC is simulated using PLECS software. The device parameters and thermal data of the selected devices are embodied into the software. The overcurrent situation is created using programmable load. The ambient temperature of 85 • C is imposed on all semiconductor devices and heat sinks. The PLECS simulation model of the SSPCs are then subjected to the all current/load situations as mentioned in Section II. A single input/single output SSPC is designed with five internal channels using CREE MOSFETs. The conduction loss of the diode (second switch's antiparallel diode) is nil because the voltage drop across the diode is not sufficient to forward bias, and eventually no current flows through it. The maximum junction temperature during nominal condition reaches up to 120 • C with a heat sink (R thca =4 • C/W). Similarly, total loss per device is around 8.2 W. If two times of the nominal current flows through the SSPC, the junction temperature reaches up to 126 • C.
Single channel IGBT based SSPCs are designed in PLECS using Mistubishi and Infineon devices for thermal analysis. The steady-state device junction temperatures for SSPCs notched up to 114 • C and 105 • C, respectively for Mitsubishi and Infineon devices. The two-second over-current (two times of the nominal current) scenario is simulated with SSPCs based on the two different devices and the maximum junction temperature of the Mitsubishi device is 117 • C and Infineon device is 108 • C (with the heat sink, R thca =0.1 • C/W).
For 500 ms pulse, the magnitude of the over-current is five times of the nominal current, the junction temperatures surge high for devices with small case area. However, Infineon device provides the best thermal stability with a maximum junction temperature of 120 • C.
The SSPC for this application is subjected to handle nine times of the nominal current for 3 ms. In addition, the worst case over-current scenario is created with all over-current staircase pulses (two consecutive staircase pulses (at 50 sec interval) of 2 times of the nominal current for 2 sec, 5 time of the nominal current for 500 ms, 9 times of the nominal current for 3 ms). The maximum junction temperatures obtained from simulation of the devices during all conditions are provided in Table V. The junction temperature of the devices obtained with simulation nearly matches the analytical results presented in the earlier section.
After two pulses of staircase over-current pulse, the max-imum junction temperatures attained by the devices are 155 • C, 174 • C, and 126 • C, respectively for CREE, Mitsubishi, and Infenion devices. Infenion device has more case area as compared with Mitsubishi/CREE's case area which allows Infenion device to easy heat dissipation during the transient condition. Moreover, it can withstand multiple over-current pulses than other devices without exceeding the junction temperature. A PLECs simulation result for CREE device is shown in Fig. 7, however other graphical results are omitted due to page constraints.

VI. NOMINAL EFFICIENCY OF THE SSPC
The semiconductor devices of SSPCs are normally on throughout its life except breaking operations. Therefore, the major loss of the SSPC is the conduction losses. The switching loss of the device is ignored while evaluating the nominal efficiency of the SSPC during the design process.
The conduction loss of MOSFET based SSPC is the sum of conduction losses of two MOSFETs per channel. During a steady state of the CREE device, antiparallel diodes are never turned on due to the very low voltage drop across the MOSFET. So, conduction loss due to the antiparallel diode is omitted from the calculation. The conduction loss (C l(mos(sspc)) ) and efficiency (η mos(sspc) ) of the MOSFETs based SSPC can be estimated as: For IGBT based SSPC, the total loss is the summation of conduction loss of a IGBT and an antiparallel diode. The total conduction loss (C l(igbt(sspc)) ) and efficiency (η igbt(sspc) ) of IGBT based SSPC can be approximated as: The IGBT based SSPC consists of two IGBT modules and cooling fan based sinks. The weights of those sinks are approximately one kg per sink. However, SiC-MOSFET based SSPC module consists of ten modules with each sink weighing 300 gms. Therefore, the cumulative weight of semiconductors and their heat sinks in case of MOSFET based modules is higher than that of IGBT based modules. In addition, a large number of devices requires more drivers and other auxiliary powering circuits leading to more weight and cost of the overall system. However, the higher switching frequency of MOSFET allows faster tripping time than that of the IGBTs. The comparison of SSPCs based on semiconductor device used is presented in Table VI. Out of three main devices, Infineon IGBT, F Z1600R17HP 4 B2, would be a suitable selection for this application due to its reasonable good reliability, tripping time, cost, weight, and volume.

VII. CONCLUSION
Four different topologies of the SSPCs suitable for high power HVDC distribution in MEA are investigated. It is found that an SSPC designed with a matrix of semiconductor devices (two devices connected with a common collector) is flexible to use IGBT/MOSFET/JFET and can be used for various power range. Three MOSFETs and IGBTs are found suitable for the design and implementation of this high power SSPC. High current and high voltage CREE MOSFETs (CAS300M12BM2/CAS325M12HM2) needs five parallel channels to withstand transient current during turnoff. Two different IGBTs (CM1400HA-24S-Mitsubishi and FZ1600R17HP4 B2-Infenion) are suitable for single channel high power SSPC. It is found that five channel MOSFET based IGBT exhibits maximum efficiency, however, the power density of MOSFET based SSPC is lower than IGBT based SSPC. Out of these three devices, FZ1600R17HP4 B2 is found to be the most suitable due to high thermal stability, reasonably good efficiency, and better power density.