A DC-DC Boost Converter with a Wide Input Range and High Voltage Gain for Fuel Cell Vehicles

— In fuel cell vehicles, the output voltage of the fuel cell source is typically much lower than the voltage required by the DC bus and also this output voltage drops significantly as the output current increases. In order to match the output voltage of the fuel cell source to the DC bus voltage, a new DC-DC boost converter with a wide input range and high voltage gain is proposed to act as the required power interface, which reduces voltage stress across the power devices and operates with an acceptable conversion efficiency. A prototype rated at 300W/400V has been developed and the maximum efficiency of the proposed converter was measured as 95.01% at 300W. Experimental results are presented to validate the effectiveness of the proposed converter.


I. INTRODUCTION
 As nonrenewable resources such as oil, gas and coal become scarce, more and more research is focused on the problem of high energy usage and society's dependence on fossil fuels [1]- [3]. Additionally, the number of automobiles continues to increase in most countries, causing a significant rise in air pollution. Vehicles powered by fuel cell sources may help to reduce transport's dependence on oil, and reduce polluting emissions [4]. The fuel cells can utilize hydrogen or natural gas, to achieve a high energy density and can potentially generate "clean" electricity with high efficiency. However, unlike batteries which have a fairly constant output voltage, the output voltage of fuel cells drops significantly with an increase of output current [5]- [7]. Hence, a step-up DC-DC converter with a wide range of voltage-gain is essential to interface between the low voltage fuel-cell source and the high voltage DC bus of the motor drive inverter. The conventional DC-DC Boost converter is one of the most commonly used topologies for stepping up voltage. In theory, when the duty cycle approaches unity, the conventional boost converter can achieve a high voltage gain [8]. However, it is difficult to implement a high voltage gain (e.g. more than 6), due to the existence of parasitic elements (stray inductance, capacitance) and the extreme duty cycle required. In addition, the power semiconductors suffer from a high voltage stress -the DC bus voltage.
In order to obtain a DC-DC Boost converter with a high voltage gain and a low voltage stress, many different topologies have been proposed by researchers [9]. These converters can be divided into two types: isolated and non-isolated converters. Isolated converters are widely used in many applications, and an arbitrarily high voltage-gain can be theoretically achieved by increasing the turns ratio of the transformer employed [10]. However, there are many situations where galvanic isolation is unnecessary, and the snubber circuit required in an isolated topology will increase the complexity of the converter design [11]- [12]. Compared with isolated converters, the cost and magnetic losses of non-isolated converters are lower. A high voltage-gain can be achieved by introducing a coupled inductor to topology e.g. [13], and the converter can maintain a low device voltage stress. However a large number of inductors is required leading to an increased volume, a higher cost, and a reduced efficiency [14]. Non-coupled inductor based converters can also be used to obtain a high voltage-gain reducing the number of magnetic devices. The conventional quadratic DC-DC boost converter in [15] can obtain a high voltage-gain, but the voltage stress across the high side power semiconductors is as high as the output-voltage. To solve this problem, the switched-capacitor (SC) configurations introduced in [16], and [17] are able to obtain a high voltage gain, but they cannot achieve flexible voltage regulation unless they are combined with other DC-DC converters [18]. A topology called the "switched-capacitor-based active-network" (SC-ANC) is presented in [19]; the voltage stress across the power semiconductors can be reduced by half, and the voltages across the output capacitors can also balance themselves naturally. However, the power switches may see a large voltage spike as a result of the leakage inductance of the circuit. The switched-capacitor circuit was studied in [20]: it achieves flexible voltage regulation by combining it with other DC-DC converters, however the difference in potential between the ground points of the input voltage source side and the load side is a high frequency PWM voltage, because instead of a common ground structure, there is a diode located between the ground points of the input voltage source side and the load side. As a result, it may introduce issues associated with du/dt and these may limit its applications [21]- [22].
The Z source DC-DC Boost converter has the potential for a high voltage gain. A Z source DC-DC converter with a cascaded switched-capacitor has been presented in [23]. This topology can improve the voltage gain of the Z source DC-DC Boost converter by using the voltage multiplier function of the switched-capacitor. However, the drawbacks of the converter are obvious, such as the penalty of the discontinuous input current and the different ground points between the input voltage source side and the load side. Moreover, the power semiconductors will see a high voltage stress when the duty cycle approaches zero. In a similar way, switched-inductor (SL) techniques can also be used in dc-dc converters to achieve a high voltage gain as presented in [24], and [25], but they often need large numbers of inductors. Therefore, the volume and cost of these converters will be increased.
To address these issues, a new non-isolated high ratio step-up dc-dc converter is proposed in this paper, which has the following features: 1) It reduces the voltage stress across the power devices and has a common ground between the input and output sides.
2) The two power switches turn on and off simultaneously. As a result, the control of the converter is simple, and power switches with low on-state resistance can be employed.
3) The system operates with a high voltage gain and a wide input voltage range and does not use any extreme values for its duty cycle. This paper is organized as follows: In Section II, the configuration and operating principles of the proposed converter are presented. The voltage gain is analyzed in Section III. In Section IV, the voltage and current stresses are calculated. The design of the components is presented in Section V and in Section VI, the dynamic modeling is established. Experimental results and analysis are presented in Section VII to validate the features of the proposed converter.

A. Configuration of the proposed converter
The high voltage gain DC-DC Boost converter is shown in Fig. 1. It comprises two active power switches (Q1 and Q2), five power diodes (D3-D7), two inductors (L1 and L2) and five capacitors (C1-C5). The fuel-cell source Uin and the inductor L1 are connected in series to charge capacitors C1 and C2 in parallel. Inductor L2 is another energy storage component which is used to realize a high voltage gain. The ladder type voltage multiplier (capacitors C3-C5 and diodes D5-D7) can improve the voltage-gain further and reduces the voltage stress across the power semiconductors on the high voltage side. Fig. 1 Topology of proposed converter.
2) Switching state II. As shown in Fig. 2(b), Q1 and Q2 turn off, C1 and C2 are charged in parallel by the DC source and L1 (i.e. Uin-L1-D3-C1, and Uin-L1-C2-D4). At the same time, C4 is charged by the DC source, L1, and L2 in series (i.e. Uin-L1-D3-L2-D5-C4). In addition, C4 and C5 are charged by the DC source, L1, L2, and C3 (i.e. Uin-L1-D3-L2-C3-D7-C5-C4), as well as through the load R. The output-voltage Uo is equal to the total voltages across C4 and C5. According to the key operating waveforms of the proposed converter shown in Fig. 3, the inductor currents iL1 and iL2 have the same energy transfer process. When S=1, power switches Q1, Q2 and diode D6 are turned on. The current iQ1 increases linearly while iQ2 and iD6 decreases linearly. The output capacitor current iC5 is negative which means C5 is discharged. When S=0, power switches Q1, Q2 and diode D6 are turned off. The currents iD5 and iC5 decrease linearly. The capacitor voltage fluctuations reflect the charging and discharging processes. It can be seen from the capacitor voltages UC2 and UC3 that capacitors C2 and C3 have the opposite charging and discharging states.

III. STEADY-STATE VOLTAGE GAIN ANALYSIS
If the switching period for the power switches is T, then, dT is the on-state period, and (1-d) T is the off-state period, where d is the duty cycle of the power switches. It is assumed that the capacitor voltage and the inductor current are constant during each switching period, and the forward voltage drop and the on-state resistance of the power semiconductors are ignored. (1) can be derived according to the volt-second balance principle for inductors L1 and L2: The voltage relationship between the output and capacitor voltages can be found, in terms of the two switching states which are shown in Fig. 2: As a result, the output voltage Uo can be obtained from (1) and (2) as follows: where M is the conversion ratio, i.e. the voltage gain. (3) shows that the proposed converter can theoretically obtain a high and wide voltage gain range. The voltage gain as a function of the duty cycle for the proposed converter has been compared to the converters in [23] and [26]- [28] and these are shown in Fig. 4. It can be concluded that the voltage gain of the proposed converter is higher than the converters in [26]- [28], especially when d>0.2. Although the converter in [23] has a better voltage gain curve, the low conversion efficiency and the non-common ground will cause more power losses and increased du/dt issues, which will be analyzed in Table III. Considering the voltage gain, the efficiency and the common ground together, the proposed converter in this paper has the advantages of a high and wide voltage gain range, an acceptable conversion efficiency, and a common ground.
Converter in [23] Converter in [28] Converter in [26] Proposed converter Converter in [27] Converter in [26] Voltage gain (M) duty cycle (d) Fig. 4 Comparisons of voltage gain as a function of the duty cycle for different converter topologies.

A. Voltage Stress Analysis
According to the analysis of each of the operation states in Fig. 2 (3), the voltage stresses across the power devices can be deduced as shown in Table I.

and the voltage gain in
Therefore, the voltage stresses across the active power switches Q1 and Q2 are less than half of the output voltage Uo. For diodes D3 and D4, the voltage stresses are less than one third of Uo, whilst the voltage stresses across D5-D7 are less than two thirds of Uo, as well as the voltage stresses across capacitors C1-C5. The voltage stresses across C1 and C2 are less than one third of Uo. The voltage stress across C4 is less than half of the output high voltage Uo, whilst the voltage stresses across C3 and C5 are less than two thirds of Uo.

B. Current Stress Analysis
Using the current analysis in Fig. 2 and Kirchhoff's current laws (KCL), the current stresses across the power devices can also be obtained as shown in Table II.
The current stresses across the power devices are related to the operating duty cycle d (usually between 0.2 and 0.4). For instance, the maximum current stress across active power switch Q2 is 7.5Io. Therefore, it can be used as a reference in the component parameters design section. Note also that the current stresses across Q1-D7 are mean values, the current stresses across capacitors C1-C5 are root mean square values.  13 (1 ) The comparison of the proposed converter with other existing high voltage gain DC-DC Boost converters is shown in Table III. It can be seen that the proposed converter achieves a high and wide voltage gain range by increasing the number of diodes by a small amount. The converter in [23] can achieve a high voltage gain when the duty cycle approaches 0.5, but the converter will suffer from a high voltage stress which is almost equal to the output voltage when the duty cycle d is close to zero. In addition, the converter in [23] has a poor efficiency compared to the other converters. Compared with the converters in [26] and [27], the proposed converter is more suitable for applications requiring a large step-up ratio. Considering the selection of the power switches, the converter in [27] will have its maximum device voltage stress (which is higher than half of the output voltage) when d≠0.5, whereas the maximum voltage stress across the power switches is less than half of the output voltage in the proposed converter. Considering the selection of the diodes, the maximum voltage stress across the diodes for the proposed converter is lower than that of the converters in [26] and [27]. Although the converter in [28] has the advantage of the lower voltage stress, it does not have a common ground between the input and the output sides and this may cause additional du/dt issues.

A. Design of the power switches and diodes
The design of the power switches and diodes should refer to the most severe conditions that the semiconductor devices will operate in. Assuming that the maximum required voltage gain is 10 and the load power is 400W, the duty cycle d and the output current Io can be obtained as follows: It can be deduced from Table I and Table II that the maximum mean voltage stresses across Q1 and Q2 are 70V and 166V respectively, and the maximum mean current stresses on Q1 and Q2 are 16.5A and 6.2A respectively. Similarly, it can be derived from Table I and Table II that the maximum mean voltage stress across D3 and D4 is 70V, which is equal to that of Q1. In addition, the maximum mean current stress on D3 and D4 is 5.8A, and the maximum mean voltage and current stresses on D5-D7 are 234V and 1.9A, respectively.

B. Design of the inductors and capacitors
Assuming that the maximum required current ripple in the inductors is L I  , the inductances can be calculated when L is in the charging state as given in (5): where LL d= Δ iI , dt=d × T=d/fs (fs is the switching frequency).The inductances of L1 and L2 can be derived as (6): If it is assumed that the maximum acceptable voltage ripple across the capacitor is C ΔU , the capacitances of the five capacitors in the proposed converter can be calculated as (7): where dt=d×T=d/fs, C i is the corresponding current flowing through the capacitor, C is the capacitance, and CC d= Δ uU .The capacitances of the five capacitors can be calculated as (8):

VI. DYNAMIC MODELING
It is assumed that the power semiconductors, inductors, and capacitors are analyzed for operation under ideal conditions. The average model and the small-signal model can be obtained by using the state-space averaging method [29]- [31]. The capacitances are set such that C1=C2=C3=C4=C5=C to simplify the analysis. The inductances are defined as L1 and L2, the load resistance is R, and uin(t), uo(t) and d are the input variable, the output variable and the control variable, respectively. iL1(t), iL2(t), uC1(t), uC2(t), uC3(t), uC4(t), and uC5(t) are the state variables. According to Fig. 2(a) When S=0, the off-state period is (1-d)  T, and the state space average model can be written as (10): Combining (9) with (10), the average model of the converter can be obtained as (11): The state variables, the input variable, the output variable and the control variable can be described by the small-signal disturbance variables as (12):  (11) and (12), the small-signal model of the converter can be written as (13): Using (13) and the experimental parameters shown in Table  IV, And the zero-pole modeling of the control-to-output transfer function can be obtained as (15): It is usually necessary to reduce the order of the dynamic model (keeping a reasonable approximation) to simplify further analysis. Therefore, (15) can be reduced to be (16) from the seventh to the fifth order by appropriate pole-zero cancellation.
The Bode diagram of the proposed converter is shown in Fig. 5. It can be seen that the curves of the original and the simplified model are approximately the same. In order to achieve stable operation, a voltage loop PI controller needs to be designed and this is now described.
Based on (16), the voltage loop control scheme for the proposed converter can be obtained as shown in Fig. 6. ' ()

ZPK
Gs is the transfer function of the converter, Gc(s) is the voltage controller transfer function (i.e. a PI controller) as shown in (17), and H(s) is the feedback transfer function. Therefore, the voltage controller can be designed for the proposed converter to achieve suitable static and dynamic performances.
For this work Kp=0.0013, and Ki=0.00033. Using this voltage loop PI controller, the bode diagram of proposed converter voltage loop is shown in Fig. 7. It can be seen that the phase margin is 50.4 degrees (i.e. greater than 0) when the gain is 0 dB, and therefore the converter can theoretically achieve stable operation.

VII. EXPERIMENTAL RESULTS AND ANALYSIS
In order to validate the feasibility and effectiveness of the proposed converter, a 300W experimental prototype has been developed as shown in Fig. 8. The parameters of the experimental converter are listed in TABLE IV. An adjustable dc source with a range of Uin=40V~120V is used to emulate the fuel cell stack source. The voltage loop of the converter is controlled by a TMS320F28335 DSP controller. Hybrid power switches (MOSFETs IRFP250N and IXTH88N30P) are employed in the low and the high voltage sides, respectively. DSEC60-03A diodes are used on the low voltage side and DPF60IM400HB diodes are used on the high voltage side. In addition, the switching frequency is 20 kHz, the inductors are L1=330μH and L2=1mH respectively (the inductances are increased to keep the current continuous), the electrolytic capacitances are C1=C2=540μF, and the film capacitances are C3=C5=20μF, C4=40μF. The input voltage Uin is variable from 40V to 80V, the reference output voltage is 400V, and the load resistance is R=533Ω (i.e. the rated power=300W). The voltage stresses across Q1 and Q2 and the inductor current iL1 in the steady state are shown in Fig. 9, when Uin=40V, and Uo=400V. From Fig. 9(a), it is clear that when UQ1=0, iL1 increases linearly. When UQ1≈65V, iL1 decreases linearly. The average value of iL1 is about 8A while the ripple rate is about 12.5%. Similarly, Fig. 9(b) shows that the inductor current iL2 has the same trend as iL1: the average value of iL2 is approximately 3.5A, and the voltage stress across Q2 is 165V, which is less than half of the output-voltage (400V). The input-voltage and the output-voltage are shown in Fig. 10 where the voltage-gain is 10, and it can be seen that the proposed converter can achieve a high voltage gain. Fig. 10(a) shows the simulated result and Fig. 10(b) shows the experimental result. Furthermore, according to Fig. 10(a), the duty cycle d in the simulation is 0.42. Thus, the duty cycle d in the experimental result is also approximately 0.42 -a good correlation. The voltage stresses across the low voltage diodes D3 and D4 are shown in Fig. 11. It is clear that the voltage stresses across D3 and D4 are low -the same as UQ1. The voltage stress across the high side diodes, and the output voltage are shown in Fig. 12. It can be seen that all the voltage stresses across the high side diodes D5-D7 are equal, and are about half of the output voltage.   The voltage loop control maintains the output-voltage at 400V in the steady state. In addition, the output voltage can still be kept at 400V even when the input voltage changes significantly, which can be seen in Fig. 13, where the input voltage is changed from 80V to 40V over 16 seconds and the output voltage stays at approximately 400V (i.e. a voltage-gain increase from 5 to 10). Therefore, the proposed converter can realize a high step-up ratio and a wide step-up voltage gain range during dynamic operation with a variable input voltage.
The conversion ratio is an important parameter which reflects the actual operating performance of the converter. Based on (3), Fig. 14 shows the gain curves derived from theory and from the experimental measurements. Neglecting the parasitic impedances, the theoretical curve is calculated using (3) and is in general higher than the experimentally measured curve for different duty cycles (0.2-0.5).The measured gain curve has a good match with the theoretical curve, which shows the practicability of the proposed converter from an experimental perspective. The efficiency measured by a Power Analyzer (Yokogawa-WT3000) with different voltage-gains is shown in Fig. 15: the output voltage is Uo=400V, and the output power Po varies from 200W to 400W. The maximum efficiency is 95.01%, when Uin=80V, and Po=300W, i.e. the voltage-gain is 5. The minimum efficiency is 90.06%, when Uin=40V, and Po=400W, i.e. the voltage-gain is 10. The efficiency decreases as the voltage gain increases, because the increase in input current causes larger switching losses. The calculated loss distribution [32] for the experimental system for Uin=40V, Uo=400V, and Po=300W are shown in Fig. 16. The total losses of the proposed converter are 24.6W. The turn-on and turn-off (switching) losses of the power switches Q1 and Q2 (i.e. P2=7.36W) account for 30% of the total losses. The conduction losses of all diodes D3-D7 (i.e. PD=3.97W) account for 16% of the total losses, which is nearly equal to the conduction loss of power switches Q1 and Q2 (i.e. PQ=3.9W). In addition to the conduction losses of the semiconductors, the copper losses PCu of inductors L1 and L2 are 4.07W, which account for 16% of the total losses. The core losses of inductors L1 and L2 (i.e. PFe=4.36W) account for 18% of the total losses. The capacitor losses of C1-C5 are PC=0.94W, which account for 4% of the total losses.

VIII. CONCLUSION
A high voltage gain DC-DC Boost converter with a wide input range, continuous input current and common ground points between the input side and the load side has been proposed in this paper. The voltage stress across the main power switches is lower than half of the output voltage. In addition, the proposed converter can keep the output voltage at 400V using a voltage control loop, when the input voltage changes from 80V to 40V. Therefore, it is suitable for the power interface between a fuel cell source and the DC bus for the motor drive in fuel cell vehicles.