High-temperature validated SiC power MOSFET model for flexible robustness analysis of multi-chip structures

This paper presents a statistical analysis on the effect of parallel connection of SiC power MOSFETs in high current applications. To this purpose, a reliable temperature-dependent SPICE model is calibrated on static and dynamic experimental curves of 1.2kV-36A commercial SiC MOSFET. The statistical fluctuation of threshold voltage and on-resistance is evaluated on 20 device samples and modeled with Gaussian functions. The proposed analysis, based on SPICE electrothermal Monte Carlo simulations, is then aimed to improve the design of high current systems with multi-chip devices. Therefore, the study is focused on the evaluation of current and energy unbalance during device switching under inductive load. Results achieved for nominal switching condition and out-of-SOA current levels are discussed.


INTRODUCTION
Silicon carbide (SiC) power MOSFETs are finding widespread adoption in many application areas, such as energy distribution, automotive and aircraft, thanks to many excellent features. In several high power applications there is the need to use parallel devices, since commercial SiC MOSFETs are mostly available for low current ratings. Although for Si MOSFETs and IGBTs paralleling is well known and commonly used in many applications [1], [2], poor information is available in literature for SiC MOSFETs. Compared to commercial SiC modules [3], the use of discrete devices in parallel has some benefits: (i) the generated heat could be more evenly distributed over the heatsink (thus reducing temperature peaks); (ii) during the design process, flexibility is gained in terms of number of devices to use; (iii) lower cost is obtained thanks to the high volume production of discrete parts.
However, when paralleling two or more SiC MOSFETs, their currents may not be balanced due to the statistical fluctuations of the on-state resistance (Ron) and threshold voltage (VTH) from sample to sample. This phenomenon can drastically reduce the reliability of the entire power system [4]. Previous works [5], [6] have suggested different feedback techniques for balancing drain currents during switching transients. However, those methods could be applied just for two parallel devices, and increase the overall system cost. In [7] an experimental study on the SiC MOSFET's selfbalancing capability without adding any sensing or control circuit is presented. The parameters used to balance paralleled devices are the gate drive voltage and resistance. However, this solution requires a tailored gate drive circuit for each device and could not be applied to modules. Another way to address this problem could be the adoption of design rules to determine the maximum allowed device parameters dispersion and parasitic circuit elements unbalance [8]. To optimize these rules, a valid approach involves a simulation analysis that quantifies the impact of device and circuit mismatches on the application performances. Since SiC MOSFETs often operate under harsh conditions, reliable electro-thermal (ET) simulations are mandatory for design optimization. In the last years, several papers have focused on the modeling of SiC MOSFETs [9]; some of them rely on empirical functions [10], while others are based on physics-based descriptions [11].
In this paper, a temperature-dependent SPICE model for SiC MOSFETs [12] is exploited for dynamic ET simulations of single and paralleled devices, both in SOA and out-of-SOA conditions. An experimental measurement campaign on 20 virtually identical devices is used to characterize the statistical distribution of RON and VTH. Finally, an analysis based on Monte-Carlo ET simulations of 4 paralleled devices during switching is presented. The impact on the statistical energy dissipation is evaluated during turn-on and turn-off transients. Lastly, the potential unbalance in temperature is discussed.

II. SIC MOSFET COMPACT MODEL
In this paper, an extended formulation of a previously presented SPICE model [13] is reported, which has been experimentally verified on a broad range of operating conditions. The schematic representation of a planar SiC MOSFET structure is depicted in Fig. 1.   The model is based on the partitioning of the device into an 'intrinsic' (channel) MOSFET, a bias-dependent resistance for the accumulation and JFET regions, and a constant resistance for the epitaxial drift region. The influence of SiO2/SiC interface traps on threshold voltage and channel mobility, impact ionization and capacitance nonlinearity are accounted for. The most relevant model equations are reported in Fig. 2, while the related SPICE sub-circuit is depicted in Fig. 3.
The parameters require a simple optimization procedure based on experimental data; the details are given in [12].

A. Model calibration and verification
The device under test (DUT) selected as a case-study is an 80 mΩ 1.2kV-36A 4H-SiC power MOSFET. The model parameters were calibrated on measurements performed at different baseplate temperatures under pulsed (isothermal) conditions. Fig. 4 and Fig. 5 show the transfer and output characteristics at 300 and 400 K. Excellent agreement was obtained with the experimental dc characteristics despite the smooth triode-saturation transition occurring in SiC transistors. A double-pulse test was used to verify the model accuracy under dynamic conditions. Both turn-on and turn-off current and voltage evolutions are well predicted, as reported in Fig. 6.

III. STATISTICAL ANALYSIS
In order to perform the Monte Carlo analysis, a statistical description of the device parameters fluctuation (Ron and VTH) is needed. To this purpose, the MOSFET current factor K and the threshold voltage VTH for all the 20 devices were directly extracted from the highest-slope portion (medium VGS) of the isothermal ID-VGS transfer characteristics measured at various baseplate temperatures using the quadratic extrapolation method (QEM). The on-state resistance was evaluated on the output ID-VDS curve for VGS=20 V.

A. Monte Carlo ET simulations
The proposed Monte Carlo analysis was based on the paralleling of 4 SiC MOSFETs in a double-pulse test. The circuit is shown in Fig. 8 along with parasitic elements and test parameters. An example of the impact of devices mismatches is reported in Fig. 9, which confirms that the individual transistor with lower Ron (MOSFET 4) conducts an higher current, while the current sharing during turn-off transient is affected by the VTH unbalance. In particular, the MOSFET with the lower VTH will switch-on earlier and switch-off later than the higher-VTH others. As a consequence, a nonuniform temperature increase takes place. As a relevant result, the MC analysis also allowed quantifying the statistical distribution of the energy dissipation during turn-on and turnoff transients as dictated by the VTH and Ron variation. The first analyzed case was for nominal device current ID=20 A, involving a total load current of 80 A. In this analysis, 1500 MC ET simulation were carried out and the histograms of the dissipated energy evaluated during turn-off and turn-on for each of the 4 MOSFETs are reported in Figs. 10 and 11, respectively. The resulting shape of statistical energy distributions were almost Gaussian with expected Eoff and Eon values of about 580 µJ and 1.3 mJ, respectively. The most useful finding is the considerable switching loss spreading in real applications. For example, derating rules for SiC MOSFETs can be extracted using these data. Another critical point regards the energy unbalance within the same multi-chip structure. Fig. 12 reports the maximum energy unbalances for each Monte Carlo simulation run, evaluated as: Pointing the attention only on the switching power loss, the unbalance in temperature rise ∆T can be estimated as:     Considering the thermal resistance Rth of the SiC MOSFET used in this paper (Rth=0.6 K/W), with a switching frequency of 80 kHz the above expressions provide a maximum temperature difference ∆T≈34 K. However, (4) just gives an indication for the design of a power system. In fact, due to the negative temperature coefficient of VTH [12], the switching loss difference will increase due to ET effects, and then a positive feedback can arise. On the other hand, the Ron increase with temperature is expected to partially compensate such temperature difference. It is desired and important to minimize the switching loss difference caused by threshold voltage variance, since the switching loss difference turns into difference in temperatures of the paralleled devices.
Lastly, in Fig. 13 a first attempt to the out-of-SOA analysis is given with the evaluation of switching loss unbalance for a total load current of 160 A (40 A × 4 MOSFETs). The results in terms of ∆Eoff and ∆Eon can be used to analyze the impact of device mismatches on the reliability of the entire power multichip module.

IV. CONCLUSION
In this work, a statistical analysis on the effect of parallel connection of SiC power MOSFETs in high-current applications has been presented. The analysis relies on a temperature-dependent SPICE model calibrated on dc and transient experimental curves of a 1.2 kV-36 A commercial SiC MOSFET. The statistical fluctuations of threshold voltage and on-resistance have been evaluated on 20 devices, and a Gaussian fitting was used to perform SPICE electro-thermal Monte Carlo simulations. The study, focused on the evaluation of current and energy unbalance during switching under inductive load, gives helpful indication on the impact of VTH and Ron statistical fluctuation in real applications.