Modelling and control of a multi-stage interleaved DC – DC converter with coupled inductors for super-capacitor energy storage system

: Interleaved converters with coupled inductors are widely used to share load current in high power applications. It offers high equivalent switching frequency and reduced output current ripples using small size magnetic components. Owing to smaller common-mode inductance, control system can be designed to achieve fast dynamic response. This study proposes eight-channel interleaved DC/DC converter for interfacing super-capacitor energy storage system to a 400 V DC voltage bus. Multi-stage interleaving magnetic circuit with two-phase coupling inductor as a building block is proposed. A methodology is developed to construct the model of the multi-stage magnetic circuit from the basic two-phase coupled inductor model. The derived model is successfully used to evaluate the system power losses and to design the magnetic circuit parameters and its current controller to ful ﬁ l the DC/DC converter steady state and dynamic performance speci ﬁ cations. A 20 kW/four stage/8-channel DC/DC converter laboratory prototype has been built to connect a super-capacitor stack to 400 V DC voltage bus. Experimental investigation validates the modelling, the system losses calculations and the design speci ﬁ cations of the system.


Introduction
Paralleling of DC-DC converters (Fig. 1a) is the most common solution in high current applications. The channels can be operated synchronously or interleaved, the latter having the advantage that harmonic cancellation takes place on the output. Hence interleaved operation can reduce the switching frequency per channel and/or the smoothing inductance but at the expense of having high circulating currents caused by the existence of inter-channel differential-mode PWM voltage.
Regarding the smoothing inductors, there are two options: † Using independent inductors [1][2][3][4]: The common-mode current ripple (which is a part share of the output current) and the differential mode current ripple (multi-channel circulating current) are equally attenuated. † Using coupled inductors or inter-cell transformers: Although coupled inductor is one of the key building block in power application from the 1920s [5], its recent application is made by Cúk in buck-boost converter [6,7]. In [8], Witulski has shown how a coupled inductor differs from normal inductor and transformer. More recently coupled inductors become more popular in interleaved parallel DC-DC application. Its application in hybrid vehicle [9], its performance analysis with soft switching technique [10], thermal behaviour study [11], parasitic ringing phenomenon in discontinuous mode of operation [12], its impact on improving efficiency and dynamic response of converters [13], associated closed-loop control techniques [14,15] and optimisation and three-dimensional integration of coupled inductors to improve system power density [16][17][18][19][20] are well reported in the literature. In paralleled converters with coupled inductors, the mutual or magnetising inductance attenuates the inter-channel circulating currents, whereas only the leakage inductance attenuates the common mode (CM) current. This means that the design of the inter-cell inductance allows tuning of the magnetising and leakage inductance such that each ripple current component can be attenuated to obtain an optimised performance (current ripple) while minimising the stress (extra loss because of switching ripple) and inductor size. Fig. 1b shows the topology of a two channel coupled inductor-based interleaved system. The coupled inductor consists of two windings whose mutual inductance L m 1 is high. The total self-inductance of each winding is L S 1 . The high mutual inductance of the coupled inductor provides high impedance to the differential-mode (DM) PWM voltage component (v a -v b ). Hence the DM switching frequency component is attenuated to a small value but the PWM CM, having a frequency of twice the switching frequency f sw , interacts only with the leakage inductance of the coupled inductor. If the inherent leakage inductance is not sufficient to limit the CM (2f sw ) current component, an additional L l 2 inductance rated for the current cumulated over two channels is required.
If a higher number of channel is required, there are few options: † Implementing a complex inter-phase transformer with multiple windings [18] which is somewhat difficult to build and will always result in a very customised solution. † Implementing a structure as in [16,19], which consists of a number of two winding coupled inductors identical to the number of channels which is much easier to manufacture. The structure achieves some degree of symmetry by inserting in each channel the windings from two different inductors interconnected with the next/previous channel in a circular succession. † Implementing a multi-stage structure [21,22], with each stage consisting of two coupled inductor windings with the common point feeding one of the coupled windings of the next stage (see Figs. 1b-d ). High dynamic performance and low switching current ripple in each channel current are the key advantage of the topology. Moreover, it provides the flexibility to extend the number of parallel channels without modifying the existing magnetics provided the total number of channels is equal to 2 k (k is an integer). In this paper, the structure will be analysed and modelled for the first time in the literature.
If the number of channels increases to four, a second stage of coupled inductors is necessary as shown in Fig. 1c, where L m 2 provides the high impedance to the differential mode component, now having a frequency 2f sw . Unless the leakage inductance present in the two stages is insufficient, an extra inductance L l 3 is added to limit the 4f sw CM component. As the number of channel increases, the number of stages (and the associated leakage inductance contained in the coupled inductors) increases which decreases the value of the final stage inductance.
In this paper, an eight-channel interleaved converter consisting of three stages of coupled inductors (Fig. 1d ) is proposed to implement a controllable interface between a super-capacitor stack and a voltage regulated DC bus. A detailed mathematical model of the multi-stage interleaved a Topology of a two channel DC-DC converter in parallel b Two interleaved channels with coupled inductor c Three-stage magnetics for four interleaved channels d Eight channel interleaved converter with coupled inductors in four stages for super-capacitor interface e Voltage v a with time DC-DC converter is derived to enable both steady state and transient analysis of the system. The model is then used to determine the harmonic current components at various stages and to calculate the various losses in the system. Finally, the step response/dynamic performance of the controller and the efficiency of the system are experimentally verified.
The organisation of the paper is as follows. Section 2 describes the modelling of the state matrices of the magnetic structure. Section 3 presents the design of the magnetic components for an eight-channel/four-stage prototype and provides a comparison of the four-stage topology with the one-, two-, three-stage topologies in terms of peak-to-peak ripple content in each stages. The design of the current controller with additional feed-forward term is explained in Section 4. Sections 5 and 6, respectively, details harmonics analysis and loss calculation in the magnetics. The experimental results and conclusion of the work are presented in Sections 7 and 8, respectively.

Modelling of the system
In this section, modelling of the multi-stage interleaved inductor structure is carried out, starting from a two-stage system and extending to the four-stage system.

Modelling of the two-stage interleaved system
The circuit diagram of the interleaved two-stage magnetics is shown in Fig. 1b where v a and v b are the inputs [the converter pole voltages with respect to the negative DC bus terminal 'O' in Fig. 1a] and i a , i b and v 0 are the three state variables. The time domain waveform of v a is shown in Fig. 1e, where T is the switching period and 'd' is the operating duty ratio. v b will have similar shape but will be shifted by 180°. The dynamic equations can be written as L S 1 is the self inductance of each winding in the coupled inductor L l 1 + L m 1 and L l 1 and L m 1 are the leakage and the mutual inductances. The state matrices A and B can be written as As the system is linear the small signal model can be written asẋ where the quantities with hat indicate the linearised small signal quantities. d a and d b are the duty ratios of channel a and b, respectively.

Modelling of the three-and four-stage interleaved system
These stages are considered in order to establish an awareness of the symmetries involved in the final evaluation. The state matrices for the three-stage system (Fig. 1c) can be obtained as The state variables and input to the system are T , respectively. Again the small www.ietdl.org signal model can be written aṡ If r 1 , r 2 , r 3 and r 4 are the resistances of the coils in the respective stages in the power circuit (Fig. 1d ), the state matrices for the four-stage system can be derived as (see (8)) The state variables and input to the system are respectively. The small signal model of the system iṡ In the subsequent sections, the above model (8)-(11) will be used and/or approximated to design the magnetics, its current controller and to calculate the harmonic losses in it.

Design of the magnetics for the four-stage structure
For the super-capacitor application there are eight channels in parallel to share the total current. In this section, the magnetic components for this topology are designed. The design is based on the restriction of equal maximum peak-to-peak circulating current ripple in the coupled stages (stage-1, stage-2 and stage-3) and the maximum peak-to-peak ripple in stage-4. From (8), (9) and Fig. 1d, ignoring the effect of resistances we can write If the circulating current in the first stage is separated,  (12) becomes Similarly, the circulating current in stage-2 and stage-3 can be expressed as Again, the final stage current can be expressed from (8) and (9) as Now, for different duty ratios d, the peak-to-peak ripple in the circulating currents ΔIc 1 , ΔIc 2 , ΔIc 3 and in the total current ΔIc 4 can be expressed as In the above equations, the pattern of ΔIc 3 and ΔI 4 repeats for the remaining range of duty ratio (not shown). T s is the switching period. The expression of maximum peak-to-peak ripple in each stage (ΔIc 1max , ΔIc 2max , ΔIc 3max and ΔI 4max ) can easily be derived. With design constraint ΔIc 1max = ΔIc 2max = ΔIc 3max = ΔI 4max = ΔI = 2A, the inductance requirement in each stage can be evaluated as In order to complete the inductor design, it is important to evaluate the currents that produce the maximum flux densities in the cores of each stage (I 1m , I 2m , I 3m , I 4m ) and the RMS winding currents through each stage (I 1 rms , I 2 rms , I 3 rms , I 4 rms ). The values of these currents at the worst case operating condition can be represented as where I z is the cumulative DC current component. Finally, the area product of each inter-cell transformer (for the first three stages) and the inductor for the final stage can be obtained as where the inductance L = 4L m 1 , 4L m 2 , 4L m 3 , L l 4 , the peak current I m = I 1m , I 2m , I 3m , I 4m and the RMS currnet I rms = I 1 rms , I 2 rms , I 3 rms , I 4 rms , respectively, for the stage-1, stage-2, stage-3 and stage-4 inductor design. A c and A w are the cross-section and window area of the core, K w is the window fill factor, B m and J are the peak flux density and current density, respectively. From (23) the magnetic cores are selected. The number of turns (n T ) and air gap (l g ) can be selected as follows www.ietdl.org where μ 0 is the permeability of the air. The designed air gap needs to be tuned to obtain the desired inductance. The details of the inductor values (measured by high precision digital RLC meter PSM1735) are listed in Table 2 in the Appendix.

Comparison of one-, two-, three-and four-stage structure
In this section, the performance in terms of peak-to-peak ripple current in each channel winding of the various stages is compared of the one-, two-, three-, four-stage structures (shown in Fig. 2). For the one-stage case of Fig. 2a, there are eight separate inductors. The coefficient of the B matrix in (9) can be easily derived as, N 0 = (1/(8L l 1 )) and N 1 = N 2 = N 3 = 0. Using the same methodology used in the last subsection for the four-stage topology, the peak-to-peak inductors current ripple (ΔI 1 ) and the peak-to-peak ripple in the cumulated current (ΔI 2 ) can be derived. Fig. 3a shows these peak-to-peak ripple currents with variation in duty ratio. Similarly, for the two-, three-, four-stage case, the same parameters are plotted with duty cycle in Figs. 3b-d, respectively. For the four-stage case the peak-to-peak ripple in each channel current can be obtained by where ΔI 1 , ΔI 2 , ΔI 3 and ΔI 4 are the peak-to-peak ripple currents through consecutive stage windings. In Fig. 3, the values for various stage currents are calculated for the same peak-to-peak ripple in the cumulative current. It can be observed that with increasing number of stages the peak-to-peak ripple in all the stages decreases and the best performance is achieved with the four-stage case.

Controller design
The structure of the current controller is shown in Fig. 4a. The super-capacitor current reference I * sc is divided equally among eight channels as the reference i * a to i * h . Each channel requires an individual PI controller to prevent saturation of the magnetics. The super-capacitor voltage is added as a feed-forward term where G is the gain of the modulator plus inverter. Fig. 4b shows the generalised block diagram of the controller plus plant after the feed-forward addition. The output of each PI controller (duty ratio signal) is passed through the control to total current transfer function [say, ((I sc (s))/(D a (s)))]. The total current i sc is obtained by summing the contributions from each channel. The channel currents can be obtained by multiplying F a , F b , …, F h with  The control transfer function ((I sc (s))/(D a (s)))) can be evaluated from (8) and (9) as follows where C a is defined as [1 1 1 1 1 1 1 1 0] in y = C a x to make y = i sc and B a is the first column of B in (9) (corresponding to channel a duty ratio d a ). Now because of the super-capacitor voltage feed forward addition, there is no effect of v 0 on the current dynamics; hence the order of the system matrix A reduces to 8 (eight) and (26) can be calculated as The control functions for the other channels will be same as (27). The overall closed-loop transfer function can be written as where the definitions of W a (s),…, W h (s) are shown in Fig. 4b.
As W a (s) = W b (s) = … = W h (s), (28) reduces to Thus the control diagram is simplifies to that of Fig. 4c where the delay of the controller is considered. The open-loop control transfer function can be written as where e −sT d models the delay of the controller, k p and T i are the PI controller gain and time constant, respectively. The consideration of delay e −sT d imposes a limitation on the controller bandwidth and the stability of the system (as considered in [23]). Please note that Wa(s) and OL(s) are the same transfer function except that OL(s) considers the delay. At the crossover frequency ω c the open-loop system should have unity gain and a specified phase margin φ m .
In (31) and (32), the approximations are justified as v c SL l ≫ Sr. With φ m = 0, (31) and (32) can be solved for a given T i [the value of Ti is given in Appendix (Table 3)]. k p is turns out to be 0.0696 (k pmax ). This k p corresponds to the absolute limit of stability. It can be observed from the Bode plot of OL(s) with k p = 75 mΩ > k pmax in Fig. 5a that the phase margin is negative. However, a slightly smaller value of k p ( = 50 mΩ) provides stable operation but results in larger overshoots. A target phase margin (φ m = (π/4)) can be achieved with k p = 0.0258 [from (31) and (32)]. The observation can also be made from the Bode plot in Fig. 5a with k p = 25 mΩ. In order to verify the above observations a simulation model is studied in MATLAB. In the simulation, the plant of eight-channel four-stage topology in Fig. 1d and the controller in Fig. 4a are modelled and the equally phase shifted carriers are used to achieve proper ripple cancellation. A step change in the total current reference I * sc is made and the current response is observed with different k p values. In these simulation results, I a , I b , …, I h are the individual channel currents, V ca is the output of one of the current controllers, I sc is the combined total current.  www.ietdl.org shows the simulation result with k p = 25 mΩ which corresponds to a stable operating point. In steady state, V ca is free from oscillation which is consistent with the damped response. Fig. 5c shows the transient response that corresponds to k p = 50 mΩ. Transiently, the current rises faster than that with k p = 25 mΩ but experiences a slight oscillation at steady state. This is because of small the phase margin of the system. Although this operating point is stable, the small phase margin can cause a low-frequency oscillation in the inductor currents resulting in incomplete ripple cancellation and even saturation. Hence this operating point is not optimal in terms of magnetic component stress and leg current balancing. Finally with k p = 75 mΩ, the system goes unstable as seen in Fig. 5d. At this stage, the continuous operation of the controller is lost and it operates in a similar manner to a bang-bang controller. Fig. 6a shows the Bode plot of the closed-loop transfer function of the system I sc (s) / I * sc (s) . The measured closed-loop gains and phase shifts at various discrete frequencies are also shown in this figure. The measured values from simulation and experiment are quite close to the analytical values and a slight deviation will not be a serious issue as the designed phase margin (46.3°) and gain margin (9.1 dB) are quite high.
The step responses for different load variations are shown in Fig. 6b. Four different step responses are shown with −50 A →−20 A, −50 A → 0 A, −50 A → 20 A and −50 A → 50 A reference changes. The effect of parameter variation on stability is shown in Fig. 6c. ΣL l and Σr are varied ±20% to observed the effect on phase margin with the same designed value of the control parameters. It can be seen that there is no effect on the phase margin with resistance variations and a 20% decrease of inductance leads to a phase margin of 41°(which is still a good phase margin). In Fig. 6c, the system is still symmetric as the the variations in ΣL l and Σr are considered in symmetrical manner. However, in reality the variation may occur in one particular channel to make the system non-symmetric. In case of non-symmetrical system the mathematical description become extremely complicated hence computer programming can only handle such situation. A case study of non-symmetrical situation is shown in Fig. 6d where it is assumed that channel-h leakage inductance is different (±20%) from the other channels. With this variation the eighth columns of matrices A and B [in (8) and (9)] obtain changed form their original values. It can be seen that the variations in the Bode plots of the open-loop system are very small and the phase margin is 45.8°with 20% smaller inductance.

Harmonics analysis
In this section, the harmonic components of the applied voltages (v a , v b , v c , v d , v e , v f , v g , v h ) are determined to obtain the expressions of the various current harmonics in different stages of the system.
where ω 0 = (2π/T ). All the components a 0 , a n , b n are same for Step response with different load variations c Effect of symmetrical parameter variation on stability d A case study: effect of non-symmetrical parameter variation on stability www.ietdl.org

Calculation of current harmonics
From (8) and (9) ignoring the effect of resistances we can write where k = 0 and N x = N 0 + N 1 cos(nπ) + 2N 2 cos((nπ)/(2))) + 4N 3 cos((nπ)/(2)))cos((nπ)/(4))) and Similarly the second-stage currents (see Fig. 1d ) can be calculated as (see (39)) The third-and fourth-stage currents (see Fig. 1d ) can be expressed as (see (40)) Equations (38)-(40) represent the time domain expressions of the current at various stages of the power circuit in terms of the individual Fourier coefficients. In next subsection, this expressions will be used to evaluate the RMS expressions of the currents in each stage.

RMS expressions of the currents in terms of duty ratio 'd'
The expressions of nth harmonics in the first-stage current can be expressed as

Loss calculation in the magnetics
The inductances and high frequency resistances of the implemented magnetics are given in Tables 2 and 5 in Appendix. The details of the core materials are listed in Table 4. These parameters are used in conjunction with the expressions derived in the previous section to calculate copper and core losses in the magnetics.

Conduction loss
In the first-stage conduction loss can be expressed as The factor 8 is due to the fact that there are 8 channels. In this  Fig. 8a shows the variations of conduction loss in various stages because of high frequency currents. It is interesting to note that the conduction loss depends on operating duty ratio of the system.

Core loss
The core loss is dependent on the magnetising current that is responsible for flux in each stage. This magnetising current is nothing but the circulating current (as mentioned in Section 3). From (13), the nth component in the magnetising current in stage-1 can be written as Similarly, for the second and third stage the nth component of the magnetising current can be expressed as For stage-4, as it is a normal inductor (not coupled) where M is the mass of the core in kg; T u1 is the number of turns that produces the main working flux in the core (stage-1); f sw is the switching frequency; and A c is the core cross-sectional area. The core losses for the other stages can be calculated in similar manner. These losses are plotted in Fig. 8b for various duty ratios. The high frequency losses (core loss + high frequency conduction loss) in the magnetics is plotted in Fig. 8c.

Experimental investigation
In order to validate the proposed converter model and the associated control algorithm an experimental prototype of a 20 kW four-stage/eight-channel interleaved DC-DC converter designed as a part of a super-capacitor interface system is tested under both transient and steady-state loading conditions. The photograph of the power circuit is shown in Fig. 9. The entire super-capacitor panel with power circuit and super-capacitor stack is shown in Fig. 9a. Fig. 9b is the zoomed view of the power circuit with various coupled inductor stages. The construction of one coupled inductor (second stage) is shown in Fig. 9c. A floating point DSP-FPGA-based digital control platform (development platform C6713 DSK-based on Texas Instruments TMS320C6713 DSP + Actel Proasic3 A3P400-PQG208 FPGA board) able to perform very fast A/D conversion (eight inductor currents, DC bus and capacitor voltages) and generate sufficient PWM signals is used to implement the closed-loop control action as described in the previous section. Fig. 10 shows the measured peak-to-peak current ripple against duty ratio (from 0.5 to 0.9). The calculated values for the relevant channel of different stages are shown. It can be observed that the measured values are very close to the predicted values (Fig. 3d ) which validates the peak-peak ripple calculation of Section 3. Fig. 11a shows the system performing a 20 kW constant power charge/discharge cycling of the super-capacitor stack. The super-capacitor voltage (V sc ) was set between 250 and 350 V and the DC-link voltage (V dc ) is maintained at 400 V. The waveform of the cumulated interleaved converter current drawn from the super-capacitor stack shows a very small relative ripple which confirms that the design of the multi-stage smoothing filter was very effective. As the super-capacitor voltage is not fixed the operating duty cycle of the converter also changes with time. Hence, the direct measurement of efficiency at various power level is not straight-forward and an alternative efficiency namely, round-trip efficiency [25] of the converter is evaluated. The round-trip efficiency accounts for the energy returned from an energy storage system relative to the energy that was put in. It is therefore a multiplication of the conversion efficiencies for charging and discharging [25]. The measured values of Vsc, Isc, Vdc and Idc are stored in a personal computer and then the energy in and energy out in  Fig. 10 Comparison between calculated and measured ripple current a Peak-to-peak ripple in stage-1 channel current b Peak-to-peak ripple in stage-2 channel current c Peak-to-peak ripple in stage-3 channel current d Peak-to-peak ripple in stage-4 channel current www.ietdl.org one charge/discharge cycle is calculated by integrating the instantaneous powers (P sc = V sc × I sc , P dc = V dc × I dc ). The round-trip efficiency of the super-capacitor stack and that of DC-DC converter plus super capacitor are shown in Fig. 11b for various power levels used for charge/discharge cycling. The round-trip efficiency of the DC-DC converter alone can be obtained from these efficiencies and shown in Fig. 11c with the calculated round-trip efficiency. The calculation of round-trip efficiency includes the high frequency losses in the magnetics (detailed in Section 6), the DC losses in the magnetics (DC resistances given in Table 5), semiconductor losses (calculated from the data  sheet [26] of the semiconductor in the power circuit) and stand-by losses in the power circuit (like losses in the bleeder resistors). The round-trip efficiency of ≥ 96% is obtained in the 40-100% of the power range. At full load, the percentage contribution of the various losses in the round-trip efficiency calculation of the DC-DC converter is listed in Table 1.
Next the transient performance of the current controller designed on the proposed methods is verified by varying the gains of the PI controller around the point where the proposed model predicts instability. Figs. 12a-c show the current response of the current to a small step change in the current reference for k p = 75 mΩ, k p = 50 mΩ, k p = 25 mΩ. I sc is the total super-capacitor current and I a and I b are currents in channel-a and channel-b, respectively. The small step change is chosen to avoid the saturation and anti-wind up of the PI controller that can affect the oscillation resulting from the true dynamics of the controller. It can be noticed from Fig. 12a that while reaching the faster rising time the system becomes marginally unstable at k p = 75 mΩ which is consistent with the observation in the previous section. A k p = 50 mΩ provides an under damped response with a rise time of 100 μs but with a large settling time. This may pose an additional stress on the magnetics and the power devices. Using a smaller gain (k p = 25 mΩ in Fig. 12c) still results in a fast response (rise time: 120 μs) but with very stable output and small overshoot. Fig. 12d shows the transient response with a large current step ( −50 A → 50 A) with k p = 25 mΩ. It can be seen that the channel current sharing (in channel-a and channel-b) is quite accurate during transients and steady state.

Conclusion
This paper presents the modelling, the selection of multi-stage filter parameters, the controller design and the implementation of a multi-staged coupled inductor-based interleaved converter for high current DC-DC interface for a super-capacitor system. The multi-stage coupled inductor-based system is analysed and modelled to demonstrate the key advantages like high dynamic performance and low switching current ripple in each channel current. It improves the dynamic performance of the system as only leakage inductance is seen by the total current and a flexible choice of peak-to-peak ripple current can be done in each stage of the magnetics. The performance comparison with lower stage topologies for the same final stage peak-to-peak current ripple reveals that the four-stage topology provides the best performance in terms of peak-to-peak current ripple in all the stages. The closed-loop controller parameters are designed from this model to ensure stability and dynamic response. To enhance loss evaluation of the system the harmonics current components are analysed and the copper and core losses in the magnetics are calculated from the proposed model. The simulation and experimental results are presented to validate the design of the magnetic component and the closed-loop controller. A round-trip efficiency of ≥ 96% is achieved at the full load.

Acknowledgment
The project this report is based on was funded by E.ON as a part of E.ON International Research Initiative. Responsibility of the content of this publication lies with the author.

References
The details of the power circuit parameters are given in Table 2. The details of the control circuit parameters are www.ietdl.org given in Table 3. The details of the material and physical construction of the magnetics are given in Table 4. The number of turns (in stage-1, stage-2 and stage-3) for each coil is half of the number of turns given in the table. Table 5 gives the details of the high frequency resistance (measured by high precision digital RLC meter PSM1735) and DC resistances (obtained by passing rated DC current and measuring voltage across it) of the various stages of the magnetics.