A Novel Repetitive Controller Assisted Phase-Locked Loop with Self-Learning Disturbance Rejection Capability for Three-Phase Grids

Tang, Mi; Bifaretti, Stefano; Pipolo, Sabino; Odhano, Shafiq; Zanchetta, Pericle

Abstract

The synchronization between the power grid and distributed power sources is a crucial issue in the concept of smart grids. For tracking the real-time frequency and phase of three-phase grids, phase-locked loop (PLL) technology is commonly used. Many existing PLLs with enhanced disturbance/harmonic rejection capabilities, either fail to maintain fast response or are not adaptive to grid frequency variations or have high computational complexity. This article, therefore, proposes a low computational burden repetitive controller (RC) assisted PLL (RCA-PLL) that is not only effective on harmonic rejection but also has remarkable steady-state performance while maintaining fast dynamic. Moreover, the proposed PLL is adaptive to variable frequency conditions and can self-learn the harmonics to be canceled. The disturbance/harmonic rejection capabilities together with dynamic and steady-state performances of the RCA-PLL have been highlighted in this article. The proposed approach is also experimentally compared to the synchronous rotation frame PLL (SRF-PLL) and the steady-state linear Kalman filter PLL (SSLKF-PLL), considering the effect of harmonics from the grid-connected converters, unbalances, sensor scaling errors, dc offsets, grid frequency variations, and phase jumps. The computational burden of the RCA-PLL is also minimized, achieving an experimental execution time of only 12 ?s .

Citation

Tang, M., Bifaretti, S., Pipolo, S., Odhano, S., & Zanchetta, P. (2020). A Novel Repetitive Controller Assisted Phase-Locked Loop with Self-Learning Disturbance Rejection Capability for Three-Phase Grids. IEEE Journal of Emerging and Selected Topics in Power Electronics, 8(2), 1870-1879. https://doi.org/10.1109/jestpe.2019.2941835

• Journal Article Type: Article
• Acceptance Date: Sep 9, 2019
• Online Publication Date: Sep 19, 2019
• Publication Date: Jun 1, 2020
• Deposit Date: Jun 10, 2020
• Publicly Available Date: Jun 10, 2020
• Journal: IEEE Journal of Emerging and Selected Topics in Power Electronics
• Print ISSN: 2168-6777
• Electronic ISSN: 2168-6785
• Publisher: Institute of Electrical and Electronics Engineers
• Peer Reviewed: Peer Reviewed
• Volume: 8
• Issue: 2
• Pages: 1870-1879
• DOI: https://doi.org/10.1109/jestpe.2019.2941835
• Keywords: Phase locked loops , Power harmonic filters , Harmonic analysis , Delays , Power electronics , Steady-state
• Public URL: https://nottingham-repository.worktribe.com/output/4373393
• Publisher URL: https://ieeexplore.ieee.org/document/8844690
• Additional Information: © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.